410 lines
8.9 KiB
C
410 lines
8.9 KiB
C
/*
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* Copyright (c) 2008 Juan Romero Pardines
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* Copyright (c) 2008 Mark Kettenis
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/param.h>
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#include <sys/ioctl.h>
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#include <sys/mman.h>
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#include <sys/types.h>
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#include <machine/sysarch.h>
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#include <machine/mtrr.h>
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#include <dev/pci/pciio.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <errno.h>
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#include <fcntl.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include "pciaccess.h"
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#include "pciaccess_private.h"
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static int pcifd;
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static int
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pci_read(int bus, int dev, int func, uint32_t reg, uint32_t *val)
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{
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struct pciio_bdf_cfgreg io;
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int err;
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bzero(&io, sizeof(io));
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io.bus = bus;
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io.device = dev;
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io.function = func;
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io.cfgreg.reg = reg;
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err = ioctl(pcifd, PCI_IOC_BDF_CFGREAD, &io);
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if (err)
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return (err);
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*val = io.cfgreg.val;
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return 0;
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}
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static int
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pci_write(int bus, int dev, int func, uint32_t reg, uint32_t val)
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{
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struct pciio_bdf_cfgreg io;
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bzero(&io, sizeof(io));
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io.bus = bus;
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io.device = dev;
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io.function = func;
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io.cfgreg.reg = reg;
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io.cfgreg.val = val;
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return ioctl(pcifd, PCI_IOC_BDF_CFGWRITE, &io);
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}
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static int
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pci_nfuncs(int bus, int dev)
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{
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uint32_t hdr;
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if (pci_read(bus, dev, 0, PCI_BHLC_REG, &hdr) != 0)
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return -1;
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return (PCI_HDRTYPE_MULTIFN(hdr) ? 8 : 1);
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}
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static int
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pci_device_netbsd_map_range(struct pci_device *dev,
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struct pci_device_mapping *map)
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{
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struct mtrr mtrr;
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int fd, error, nmtrr, prot = PROT_READ;
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if ((fd = open("/dev/mem", O_RDWR)) == -1)
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return errno;
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if (map->flags & PCI_DEV_MAP_FLAG_WRITABLE)
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prot |= PROT_WRITE;
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map->memory = mmap(NULL, map->size, prot, MAP_SHARED,
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fd, map->base);
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if (map->memory == MAP_FAILED)
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return errno;
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/* No need to set an MTRR if it's the default mode. */
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if ((map->flags & PCI_DEV_MAP_FLAG_CACHABLE) ||
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(map->flags & PCI_DEV_MAP_FLAG_WRITE_COMBINE)) {
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mtrr.base = map->base;
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mtrr.len = map->size;
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mtrr.flags = MTRR_VALID;
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if (map->flags & PCI_DEV_MAP_FLAG_CACHABLE)
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mtrr.type = MTRR_TYPE_WB;
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if (map->flags & PCI_DEV_MAP_FLAG_WRITE_COMBINE)
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mtrr.type = MTRR_TYPE_WC;
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#ifdef __i386__
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error = i386_set_mtrr(&mtrr, &nmtrr);
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#endif
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#ifdef __amd64__
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error = x86_64_set_mtrr(&mtrr, &nmtrr);
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#endif
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if (error) {
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close(fd);
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return errno;
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}
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}
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close(fd);
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return 0;
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}
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static int
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pci_device_netbsd_unmap_range(struct pci_device *dev,
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struct pci_device_mapping *map)
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{
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struct mtrr mtrr;
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int nmtrr, error;
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if ((map->flags & PCI_DEV_MAP_FLAG_CACHABLE) ||
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(map->flags & PCI_DEV_MAP_FLAG_WRITE_COMBINE)) {
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mtrr.base = map->base;
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mtrr.len = map->size;
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mtrr.type = MTRR_TYPE_UC;
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mtrr.flags = 0; /* clear/set MTRR */
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#ifdef __i386__
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error = i386_set_mtrr(&mtrr, &nmtrr);
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#endif
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#ifdef __amd64__
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error = x86_64_set_mtrr(&mtrr, &nmtrr);
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#endif
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if (error)
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return errno;
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}
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return pci_device_generic_unmap_range(dev, map);
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}
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static int
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pci_device_netbsd_read(struct pci_device *dev, void *data,
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pciaddr_t offset, pciaddr_t size, pciaddr_t *bytes_read)
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{
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struct pciio_bdf_cfgreg io;
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io.bus = dev->bus;
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io.device = dev->dev;
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io.function = dev->func;
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*bytes_read = 0;
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while (size > 0) {
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int toread = MIN(size, 4 - (offset & 0x3));
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io.cfgreg.reg = (offset & ~0x3);
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if (ioctl(pcifd, PCI_IOC_BDF_CFGREAD, &io) == -1)
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return errno;
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io.cfgreg.val = htole32(io.cfgreg.val);
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io.cfgreg.val >>= ((offset & 0x3) * 8);
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memcpy(data, &io.cfgreg.val, toread);
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offset += toread;
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data = (char *)data + toread;
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size -= toread;
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*bytes_read += toread;
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}
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return 0;
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}
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static int
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pci_device_netbsd_write(struct pci_device *dev, const void *data,
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pciaddr_t offset, pciaddr_t size, pciaddr_t *bytes_written)
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{
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struct pciio_bdf_cfgreg io;
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if ((offset % 4) == 0 || (size % 4) == 0)
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return EINVAL;
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io.bus = dev->bus;
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io.device = dev->dev;
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io.function = dev->func;
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*bytes_written = 0;
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while (size > 0) {
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io.cfgreg.reg = offset;
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memcpy(&io.cfgreg.val, data, 4);
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if (ioctl(pcifd, PCI_IOC_BDF_CFGWRITE, &io) == -1)
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return errno;
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offset += 4;
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data = (char *)data + 4;
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size -= 4;
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*bytes_written += 4;
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}
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return 0;
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}
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static void
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pci_system_netbsd_destroy(void)
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{
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close(pcifd);
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free(pci_sys);
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pci_sys = NULL;
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}
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static int
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pci_device_netbsd_probe(struct pci_device *device)
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{
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struct pci_device_private *priv = (struct pci_device_private *)device;
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struct pci_mem_region *region;
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uint64_t reg64, size64;
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uint32_t bar, reg, size;
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int bus, dev, func, err;
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bus = device->bus;
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dev = device->dev;
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func = device->func;
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err = pci_read(bus, dev, func, PCI_BHLC_REG, ®);
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if (err)
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return err;
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priv->header_type = PCI_HDRTYPE_TYPE(reg);
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if (priv->header_type != 0)
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return 0;
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region = device->regions;
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for (bar = PCI_MAPREG_START; bar < PCI_MAPREG_END;
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bar += sizeof(uint32_t), region++) {
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err = pci_read(bus, dev, func, bar, ®);
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if (err)
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return err;
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/* Probe the size of the region. */
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err = pci_write(bus, dev, func, bar, ~0);
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if (err)
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return err;
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pci_read(bus, dev, func, bar, &size);
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pci_write(bus, dev, func, bar, reg);
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if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) {
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region->is_IO = 1;
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region->base_addr = PCI_MAPREG_IO_ADDR(reg);
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region->size = PCI_MAPREG_IO_SIZE(size);
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} else {
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if (PCI_MAPREG_MEM_PREFETCHABLE(reg))
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region->is_prefetchable = 1;
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switch(PCI_MAPREG_MEM_TYPE(reg)) {
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case PCI_MAPREG_MEM_TYPE_32BIT:
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case PCI_MAPREG_MEM_TYPE_32BIT_1M:
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region->base_addr = PCI_MAPREG_MEM_ADDR(reg);
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region->size = PCI_MAPREG_MEM_SIZE(size);
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break;
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case PCI_MAPREG_MEM_TYPE_64BIT:
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region->is_64 = 1;
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reg64 = reg;
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size64 = size;
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bar += sizeof(uint32_t);
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err = pci_read(bus, dev, func, bar, ®);
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if (err)
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return err;
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reg64 |= (uint64_t)reg << 32;
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err = pci_write(bus, dev, func, bar, ~0);
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if (err)
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return err;
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pci_read(bus, dev, func, bar, &size);
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pci_write(bus, dev, func, bar, reg64 >> 32);
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size64 |= (uint64_t)size << 32;
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region->base_addr = PCI_MAPREG_MEM64_ADDR(reg64);
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region->size = PCI_MAPREG_MEM64_SIZE(size64);
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region++;
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break;
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}
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}
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}
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return 0;
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}
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static const struct pci_system_methods netbsd_pci_methods = {
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pci_system_netbsd_destroy,
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NULL,
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NULL,
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pci_device_netbsd_probe,
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pci_device_netbsd_map_range,
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pci_device_netbsd_unmap_range,
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pci_device_netbsd_read,
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pci_device_netbsd_write,
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pci_fill_capabilities_generic
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};
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int
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pci_system_netbsd_create(void)
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{
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struct pci_device_private *device;
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int bus, dev, func, ndevs, nfuncs;
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uint32_t reg;
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pcifd = open("/dev/pci0", O_RDWR);
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if (pcifd == -1)
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return ENXIO;
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pci_sys = calloc(1, sizeof(struct pci_system));
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if (pci_sys == NULL) {
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close(pcifd);
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return ENOMEM;
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}
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pci_sys->methods = &netbsd_pci_methods;
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ndevs = 0;
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for (bus = 0; bus < 256; bus++) {
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for (dev = 0; dev < 32; dev++) {
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nfuncs = pci_nfuncs(bus, dev);
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for (func = 0; func < nfuncs; func++) {
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if (pci_read(bus, dev, func, PCI_ID_REG,
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®) != 0)
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continue;
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if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID ||
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PCI_VENDOR(reg) == 0)
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continue;
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ndevs++;
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}
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}
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}
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pci_sys->num_devices = ndevs;
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pci_sys->devices = calloc(ndevs, sizeof(struct pci_device_private));
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if (pci_sys->devices == NULL) {
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free(pci_sys);
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close(pcifd);
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return ENOMEM;
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}
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device = pci_sys->devices;
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for (bus = 0; bus < 256; bus++) {
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for (dev = 0; dev < 32; dev++) {
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nfuncs = pci_nfuncs(bus, dev);
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for (func = 0; func < nfuncs; func++) {
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if (pci_read(bus, dev, func, PCI_ID_REG,
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®) != 0)
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continue;
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if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID ||
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PCI_VENDOR(reg) == 0)
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continue;
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device->base.domain = 0;
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device->base.bus = bus;
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device->base.dev = dev;
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device->base.func = func;
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device->base.vendor_id = PCI_VENDOR(reg);
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device->base.device_id = PCI_PRODUCT(reg);
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if (pci_read(bus, dev, func, PCI_CLASS_REG,
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®) != 0)
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continue;
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device->base.device_class =
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PCI_INTERFACE(reg) | PCI_CLASS(reg) << 16 |
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PCI_SUBCLASS(reg) << 8;
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device->base.revision = PCI_REVISION(reg);
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if (pci_read(bus, dev, func, PCI_SUBSYS_ID_REG,
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®) != 0)
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continue;
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device->base.subvendor_id = PCI_VENDOR(reg);
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device->base.subdevice_id = PCI_PRODUCT(reg);
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device++;
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}
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}
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}
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return 0;
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}
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