131 lines
4.6 KiB
Diff
131 lines
4.6 KiB
Diff
From 4c6f97798fe1854a32b1199c42370eac1620eebf Mon Sep 17 00:00:00 2001
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From: "H.J. Lu" <hjl.tools@gmail.com>
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Date: Fri, 28 Apr 2017 10:03:09 -0700
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Subject: x86: Set Prefer_No_VZEROUPPER if AVX512ER is available
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AVX512ER won't be implemented in any Xeon processors and will be in
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all Xeon Phi processors. Don't check CPU model number when setting
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Prefer_No_VZEROUPPER for Xeon Phi. Instead, set Prefer_No_VZEROUPPER
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if AVX512ER is available. It works with current and future Xeon Phi
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and non-Xeon Phi processors.
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* sysdeps/x86/cpu-features.c (init_cpu_features): Set
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Prefer_No_VZEROUPPER if AVX512ER is available.
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* sysdeps/x86/cpu-features.h
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(bit_cpu_AVX512PF): New.
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(bit_cpu_AVX512ER): Likewise.
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(bit_cpu_AVX512CD): Likewise.
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(bit_cpu_AVX512BW): Likewise.
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(bit_cpu_AVX512VL): Likewise.
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(index_cpu_AVX512PF): Likewise.
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(index_cpu_AVX512ER): Likewise.
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(index_cpu_AVX512CD): Likewise.
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(index_cpu_AVX512BW): Likewise.
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(index_cpu_AVX512VL): Likewise.
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(reg_AVX512PF): Likewise.
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(reg_AVX512ER): Likewise.
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(reg_AVX512CD): Likewise.
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(reg_AVX512BW): Likewise.
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(reg_AVX512VL): Likewise.
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(cherry picked from commit 1c53cb49de6d82d9469ccbd5aa0c55924502bd8b)
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diff --git a/ChangeLog b/ChangeLog
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index 4962000b47..dc49c78b8c 100644
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--- a/ChangeLog
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+++ b/ChangeLog
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@@ -1,3 +1,24 @@
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+2017-04-28 H.J. Lu <hongjiu.lu@intel.com>
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+
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+ * sysdeps/x86/cpu-features.c (init_cpu_features): Set
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+ Prefer_No_VZEROUPPER if AVX512ER is available.
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+ * sysdeps/x86/cpu-features.h
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+ (bit_cpu_AVX512PF): New.
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+ (bit_cpu_AVX512ER): Likewise.
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+ (bit_cpu_AVX512CD): Likewise.
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+ (bit_cpu_AVX512BW): Likewise.
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+ (bit_cpu_AVX512VL): Likewise.
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+ (index_cpu_AVX512PF): Likewise.
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+ (index_cpu_AVX512ER): Likewise.
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+ (index_cpu_AVX512CD): Likewise.
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+ (index_cpu_AVX512BW): Likewise.
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+ (index_cpu_AVX512VL): Likewise.
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+ (reg_AVX512PF): Likewise.
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+ (reg_AVX512ER): Likewise.
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+ (reg_AVX512CD): Likewise.
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+ (reg_AVX512BW): Likewise.
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+ (reg_AVX512VL): Likewise.
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+
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2017-04-11 Adhemerval Zanella <adhemerval.zanella@linaro.org>
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* posix/globtest.sh: Add cleanup routine on trap 0.
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diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
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index 1c714a4017..41d0be2815 100644
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--- a/sysdeps/x86/cpu-features.c
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+++ b/sysdeps/x86/cpu-features.c
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@@ -139,8 +139,6 @@ init_cpu_features (struct cpu_features *cpu_features)
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case 0x57:
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/* Knights Landing. Enable Silvermont optimizations. */
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- cpu_features->feature[index_arch_Prefer_No_VZEROUPPER]
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- |= bit_arch_Prefer_No_VZEROUPPER;
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case 0x5c:
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case 0x5f:
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@@ -226,6 +224,12 @@ init_cpu_features (struct cpu_features *cpu_features)
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cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
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|= bit_arch_AVX_Fast_Unaligned_Load;
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+ /* Since AVX512ER is unique to Xeon Phi, set Prefer_No_VZEROUPPER
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+ if AVX512ER is available. */
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+ if (CPU_FEATURES_CPU_P (cpu_features, AVX512ER))
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+ cpu_features->feature[index_arch_Prefer_No_VZEROUPPER]
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+ |= bit_arch_Prefer_No_VZEROUPPER;
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+
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/* To avoid SSE transition penalty, use _dl_runtime_resolve_slow.
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If XGETBV suports ECX == 1, use _dl_runtime_resolve_opt. */
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cpu_features->feature[index_arch_Use_dl_runtime_resolve_slow]
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diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h
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index 95f0fcff87..2ee8a0a350 100644
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--- a/sysdeps/x86/cpu-features.h
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+++ b/sysdeps/x86/cpu-features.h
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@@ -62,6 +62,11 @@
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#define bit_cpu_AVX2 (1 << 5)
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#define bit_cpu_AVX512F (1 << 16)
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#define bit_cpu_AVX512DQ (1 << 17)
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+#define bit_cpu_AVX512PF (1 << 26)
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+#define bit_cpu_AVX512ER (1 << 27)
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+#define bit_cpu_AVX512CD (1 << 28)
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+#define bit_cpu_AVX512BW (1 << 30)
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+#define bit_cpu_AVX512VL (1u << 31)
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/* XCR0 Feature flags. */
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#define bit_XMM_state (1 << 1)
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@@ -236,6 +241,11 @@ extern const struct cpu_features *__get_cpu_features (void)
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# define index_cpu_AVX2 COMMON_CPUID_INDEX_7
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# define index_cpu_AVX512F COMMON_CPUID_INDEX_7
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# define index_cpu_AVX512DQ COMMON_CPUID_INDEX_7
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+# define index_cpu_AVX512PF COMMON_CPUID_INDEX_7
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+# define index_cpu_AVX512ER COMMON_CPUID_INDEX_7
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+# define index_cpu_AVX512CD COMMON_CPUID_INDEX_7
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+# define index_cpu_AVX512BW COMMON_CPUID_INDEX_7
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+# define index_cpu_AVX512VL COMMON_CPUID_INDEX_7
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# define index_cpu_ERMS COMMON_CPUID_INDEX_7
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# define index_cpu_RTM COMMON_CPUID_INDEX_7
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# define index_cpu_FMA COMMON_CPUID_INDEX_1
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@@ -254,6 +264,11 @@ extern const struct cpu_features *__get_cpu_features (void)
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# define reg_AVX2 ebx
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# define reg_AVX512F ebx
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# define reg_AVX512DQ ebx
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+# define reg_AVX512PF ebx
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+# define reg_AVX512ER ebx
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+# define reg_AVX512CD ebx
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+# define reg_AVX512BW ebx
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+# define reg_AVX512VL ebx
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# define reg_ERMS ebx
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# define reg_RTM ebx
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# define reg_FMA ecx
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--
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2.13.1
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