668 lines
29 KiB
Diff
668 lines
29 KiB
Diff
Source: https://patchwork.kernel.org/project/linux-rockchip/patch/20211019215843.42718-2-sigmaris@gmail.com/
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Tue, 19 Oct 2021 14:58:52 -0700 (PDT)
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From: Hugh Cole-Baker <sigmaris@gmail.com>
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To: heiko@sntech.de,
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hjc@rock-chips.com
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Cc: dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org,
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linux-arm-kernel@lists.infradead.org, ezequiel@collabora.com,
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Hugh Cole-Baker <sigmaris@gmail.com>
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Subject: [PATCH v2 1/3] drm/rockchip: define gamma registers for RK3399
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Date: Tue, 19 Oct 2021 22:58:41 +0100
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Message-Id: <20211019215843.42718-2-sigmaris@gmail.com>
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linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org
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The VOP on RK3399 has a different approach from previous versions for
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setting a gamma lookup table, using an update_gamma_lut register. As
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this differs from RK3288, give RK3399 its own set of "common" register
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definitions.
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Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
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---
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Changes from v1: no changes in this patch
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drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 2 ++
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drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 24 +++++++++++++++++++--
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drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 1 +
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3 files changed, 25 insertions(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
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index 857d97cdc67c..14179e89bd21 100644
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--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
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+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
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@@ -99,6 +99,8 @@ struct vop_common {
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struct vop_reg dither_down_en;
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struct vop_reg dither_up;
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struct vop_reg dsp_lut_en;
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+ struct vop_reg update_gamma_lut;
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+ struct vop_reg lut_buffer_index;
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struct vop_reg gate_en;
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struct vop_reg mmu_en;
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struct vop_reg out_mode;
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diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
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index ca7cc82125cb..bfb7e130f09b 100644
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--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
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+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
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@@ -865,6 +865,24 @@ static const struct vop_output rk3399_output = {
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.mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3),
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};
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+static const struct vop_common rk3399_common = {
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+ .standby = VOP_REG_SYNC(RK3399_SYS_CTRL, 0x1, 22),
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+ .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
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+ .mmu_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 20),
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+ .dither_down_sel = VOP_REG(RK3399_DSP_CTRL1, 0x1, 4),
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+ .dither_down_mode = VOP_REG(RK3399_DSP_CTRL1, 0x1, 3),
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+ .dither_down_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 2),
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+ .pre_dither_down = VOP_REG(RK3399_DSP_CTRL1, 0x1, 1),
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+ .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
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+ .dsp_lut_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 0),
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+ .update_gamma_lut = VOP_REG(RK3399_DSP_CTRL1, 0x1, 7),
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+ .lut_buffer_index = VOP_REG(RK3399_DBG_POST_REG1, 0x1, 1),
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+ .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
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+ .dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18),
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+ .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
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+ .cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0),
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+};
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+
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static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = {
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.y2r_coefficients = {
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VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 0),
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@@ -944,7 +962,7 @@ static const struct vop_data rk3399_vop_big = {
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.version = VOP_VERSION(3, 5),
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.feature = VOP_FEATURE_OUTPUT_RGB10,
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.intr = &rk3366_vop_intr,
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- .common = &rk3288_common,
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+ .common = &rk3399_common,
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.modeset = &rk3288_modeset,
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.output = &rk3399_output,
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.afbc = &rk3399_vop_afbc,
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@@ -952,6 +970,7 @@ static const struct vop_data rk3399_vop_big = {
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.win = rk3399_vop_win_data,
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.win_size = ARRAY_SIZE(rk3399_vop_win_data),
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.win_yuv2yuv = rk3399_vop_big_win_yuv2yuv_data,
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+ .lut_size = 1024,
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};
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static const struct vop_win_data rk3399_vop_lit_win_data[] = {
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@@ -970,13 +989,14 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = {
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static const struct vop_data rk3399_vop_lit = {
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.version = VOP_VERSION(3, 6),
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.intr = &rk3366_vop_intr,
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- .common = &rk3288_common,
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+ .common = &rk3399_common,
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.modeset = &rk3288_modeset,
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.output = &rk3399_output,
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.misc = &rk3368_misc,
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.win = rk3399_vop_lit_win_data,
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.win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
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.win_yuv2yuv = rk3399_vop_lit_win_yuv2yuv_data,
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+ .lut_size = 256,
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};
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static const struct vop_win_data rk3228_vop_win_data[] = {
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diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
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index 0b3cd65ba5c1..406e981c75bd 100644
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--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
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+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
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@@ -628,6 +628,7 @@
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#define RK3399_YUV2YUV_WIN 0x02c0
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#define RK3399_YUV2YUV_POST 0x02c4
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#define RK3399_AUTO_GATING_EN 0x02cc
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+#define RK3399_DBG_POST_REG1 0x036c
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#define RK3399_WIN0_CSC_COE 0x03a0
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#define RK3399_WIN1_CSC_COE 0x03c0
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#define RK3399_WIN2_CSC_COE 0x03e0
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Tue, 19 Oct 2021 14:58:57 -0700 (PDT)
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From: Hugh Cole-Baker <sigmaris@gmail.com>
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To: heiko@sntech.de,
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hjc@rock-chips.com
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Cc: dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org,
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linux-arm-kernel@lists.infradead.org, ezequiel@collabora.com,
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Hugh Cole-Baker <sigmaris@gmail.com>
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Subject: [PATCH v2 2/3] drm/rockchip: support gamma control on RK3399
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Date: Tue, 19 Oct 2021 22:58:42 +0100
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Message-Id: <20211019215843.42718-3-sigmaris@gmail.com>
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Errors-To:
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linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org
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The RK3399 has a 1024-entry gamma LUT with 10 bits per component on its
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"big" VOP and a 256-entry, 8 bit per component LUT on the "little" VOP.
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Compared to the RK3288, it no longer requires disabling gamma while
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updating the LUT. On the RK3399, the LUT can be updated at any time as
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the hardware has two LUT buffers, one can be written while the other is
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in use. A swap of the buffers is triggered by writing 1 to the
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update_gamma_lut register.
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Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
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---
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|
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Changes from v1: Moved the vop_crtc_gamma_set call to the end of
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vop_crtc_atomic_enable after the clocks and CRTC are enabled.
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|
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 105 +++++++++++++-------
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1 file changed, 71 insertions(+), 34 deletions(-)
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diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
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index ba9e14da41b4..e2c97f1b26da 100644
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--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
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+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
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@@ -9,6 +9,7 @@
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|
#include <linux/delay.h>
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|
#include <linux/iopoll.h>
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|
#include <linux/kernel.h>
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|
+#include <linux/log2.h>
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|
#include <linux/module.h>
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|
#include <linux/of.h>
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|
#include <linux/of_device.h>
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|
@@ -66,6 +67,9 @@
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#define VOP_REG_SET(vop, group, name, v) \
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vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
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|
|
|
+#define VOP_HAS_REG(vop, group, name) \
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|
+ (!!(vop->data->group->name.mask))
|
|
+
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|
#define VOP_INTR_SET_TYPE(vop, name, type, v) \
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|
do { \
|
|
int i, reg = 0, mask = 0; \
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|
@@ -1204,17 +1208,22 @@ static bool vop_dsp_lut_is_enabled(struct vop *vop)
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return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en);
|
|
}
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|
|
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+static u32 vop_lut_buffer_index(struct vop *vop)
|
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+{
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+ return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index);
|
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+}
|
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+
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static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc)
|
|
{
|
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struct drm_color_lut *lut = crtc->state->gamma_lut->data;
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- unsigned int i;
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+ unsigned int i, bpc = ilog2(vop->data->lut_size);
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|
|
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for (i = 0; i < crtc->gamma_size; i++) {
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u32 word;
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|
|
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- word = (drm_color_lut_extract(lut[i].red, 10) << 20) |
|
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- (drm_color_lut_extract(lut[i].green, 10) << 10) |
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- drm_color_lut_extract(lut[i].blue, 10);
|
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+ word = (drm_color_lut_extract(lut[i].red, bpc) << (2 * bpc)) |
|
|
+ (drm_color_lut_extract(lut[i].green, bpc) << bpc) |
|
|
+ drm_color_lut_extract(lut[i].blue, bpc);
|
|
writel(word, vop->lut_regs + i * 4);
|
|
}
|
|
}
|
|
@@ -1224,38 +1233,66 @@ static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc,
|
|
{
|
|
struct drm_crtc_state *state = crtc->state;
|
|
unsigned int idle;
|
|
+ u32 lut_idx, old_idx;
|
|
int ret;
|
|
|
|
if (!vop->lut_regs)
|
|
return;
|
|
- /*
|
|
- * To disable gamma (gamma_lut is null) or to write
|
|
- * an update to the LUT, clear dsp_lut_en.
|
|
- */
|
|
- spin_lock(&vop->reg_lock);
|
|
- VOP_REG_SET(vop, common, dsp_lut_en, 0);
|
|
- vop_cfg_done(vop);
|
|
- spin_unlock(&vop->reg_lock);
|
|
|
|
- /*
|
|
- * In order to write the LUT to the internal memory,
|
|
- * we need to first make sure the dsp_lut_en bit is cleared.
|
|
- */
|
|
- ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop,
|
|
- idle, !idle, 5, 30 * 1000);
|
|
- if (ret) {
|
|
- DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n");
|
|
- return;
|
|
- }
|
|
+ if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) {
|
|
+ /*
|
|
+ * To disable gamma (gamma_lut is null) or to write
|
|
+ * an update to the LUT, clear dsp_lut_en.
|
|
+ */
|
|
+ spin_lock(&vop->reg_lock);
|
|
+ VOP_REG_SET(vop, common, dsp_lut_en, 0);
|
|
+ vop_cfg_done(vop);
|
|
+ spin_unlock(&vop->reg_lock);
|
|
|
|
- if (!state->gamma_lut)
|
|
- return;
|
|
+ /*
|
|
+ * In order to write the LUT to the internal memory,
|
|
+ * we need to first make sure the dsp_lut_en bit is cleared.
|
|
+ */
|
|
+ ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop,
|
|
+ idle, !idle, 5, 30 * 1000);
|
|
+ if (ret) {
|
|
+ DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n");
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ if (!state->gamma_lut)
|
|
+ return;
|
|
+ } else {
|
|
+ /*
|
|
+ * On RK3399 the gamma LUT can updated without clearing dsp_lut_en,
|
|
+ * by setting update_gamma_lut then waiting for lut_buffer_index change
|
|
+ */
|
|
+ old_idx = vop_lut_buffer_index(vop);
|
|
+ }
|
|
|
|
spin_lock(&vop->reg_lock);
|
|
vop_crtc_write_gamma_lut(vop, crtc);
|
|
VOP_REG_SET(vop, common, dsp_lut_en, 1);
|
|
+ VOP_REG_SET(vop, common, update_gamma_lut, 1);
|
|
vop_cfg_done(vop);
|
|
spin_unlock(&vop->reg_lock);
|
|
+
|
|
+ if (VOP_HAS_REG(vop, common, update_gamma_lut)) {
|
|
+ ret = readx_poll_timeout(vop_lut_buffer_index, vop,
|
|
+ lut_idx, lut_idx != old_idx, 5, 30 * 1000);
|
|
+ if (ret) {
|
|
+ DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n");
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ /*
|
|
+ * update_gamma_lut is auto cleared by HW, but write 0 to clear the bit
|
|
+ * in our backup of the regs.
|
|
+ */
|
|
+ spin_lock(&vop->reg_lock);
|
|
+ VOP_REG_SET(vop, common, update_gamma_lut, 0);
|
|
+ spin_unlock(&vop->reg_lock);
|
|
+ }
|
|
}
|
|
|
|
static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
|
|
@@ -1305,14 +1342,6 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
|
|
return;
|
|
}
|
|
|
|
- /*
|
|
- * If we have a GAMMA LUT in the state, then let's make sure
|
|
- * it's updated. We might be coming out of suspend,
|
|
- * which means the LUT internal memory needs to be re-written.
|
|
- */
|
|
- if (crtc->state->gamma_lut)
|
|
- vop_crtc_gamma_set(vop, crtc, old_state);
|
|
-
|
|
mutex_lock(&vop->vop_lock);
|
|
|
|
WARN_ON(vop->event);
|
|
@@ -1403,6 +1432,14 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
|
|
|
|
VOP_REG_SET(vop, common, standby, 0);
|
|
mutex_unlock(&vop->vop_lock);
|
|
+
|
|
+ /*
|
|
+ * If we have a GAMMA LUT in the state, then let's make sure
|
|
+ * it's updated. We might be coming out of suspend,
|
|
+ * which means the LUT internal memory needs to be re-written.
|
|
+ */
|
|
+ if (crtc->state->gamma_lut)
|
|
+ vop_crtc_gamma_set(vop, crtc, old_state);
|
|
}
|
|
|
|
static bool vop_fs_irq_is_pending(struct vop *vop)
|
|
@@ -2125,8 +2162,8 @@ static int vop_bind(struct device *dev, struct device *master, void *data)
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
if (res) {
|
|
- if (!vop_data->lut_size) {
|
|
- DRM_DEV_ERROR(dev, "no gamma LUT size defined\n");
|
|
+ if (vop_data->lut_size != 1024 && vop_data->lut_size != 256) {
|
|
+ DRM_DEV_ERROR(dev, "unsupported gamma LUT size %d\n", vop_data->lut_size);
|
|
return -EINVAL;
|
|
}
|
|
vop->lut_regs = devm_ioremap_resource(dev, res);
|
|
|
|
From patchwork Tue Oct 19 21:58:43 2021
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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X-Patchwork-Submitter: Hugh Cole-Baker <sigmaris@gmail.com>
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X-Patchwork-Id: 12571181
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Tue, 19 Oct 2021 14:58:59 -0700 (PDT)
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From: Hugh Cole-Baker <sigmaris@gmail.com>
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To: heiko@sntech.de,
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hjc@rock-chips.com
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Cc: dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org,
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linux-arm-kernel@lists.infradead.org, ezequiel@collabora.com,
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Hugh Cole-Baker <sigmaris@gmail.com>
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Subject: [PATCH v2 3/3] arm64: dts: rockchip: enable gamma control on RK3399
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Date: Tue, 19 Oct 2021 22:58:43 +0100
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Message-Id: <20211019215843.42718-4-sigmaris@gmail.com>
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Define the memory region on RK3399 VOPs containing the gamma LUT at
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base+0x2000.
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Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
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---
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Changes from v1: no changes in this patch
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arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
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index 3871c7fd83b0..9cbf6ccdd256 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
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@@ -1619,7 +1619,7 @@ i2s2: i2s@ff8a0000 {
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vopl: vop@ff8f0000 {
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compatible = "rockchip,rk3399-vop-lit";
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- reg = <0x0 0xff8f0000 0x0 0x3efc>;
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+ reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>;
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interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
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assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
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assigned-clock-rates = <400000000>, <100000000>;
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@@ -1676,7 +1676,7 @@ vopl_mmu: iommu@ff8f3f00 {
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vopb: vop@ff900000 {
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compatible = "rockchip,rk3399-vop-big";
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- reg = <0x0 0xff900000 0x0 0x3efc>;
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+ reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
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assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
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assigned-clock-rates = <400000000>, <100000000>;
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