131 lines
4.6 KiB
Diff
131 lines
4.6 KiB
Diff
Patches for musl taken from Alpine linux: https://git.alpinelinux.org/aports/commit/?id=8a1ae17d4a9af54285c7891a680620e7e24c6280
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--- old/src/hotspot/os_cpu/linux_x86/os_linux_x86.cpp
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+++ new/src/hotspot/os_cpu/linux_x86/os_linux_x86.cpp
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@@ -90,6 +90,126 @@
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#define SPELL_REG_FP "ebp"
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#endif // AMD64
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+// ==============================================================================
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+// Taken from glibc 2.28
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+// source: https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/x86/fpu_control.h;h=4cb98c5679b2897ff4e5826d228cba6be589e24d;hb=3c03baca37fdcb52c3881e653ca392bba7a99c2b
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+// ==============================================================================
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+#ifndef AMD64
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+/* FPU control word bits. x86 version.
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+ Copyright (C) 1993-2018 Free Software Foundation, Inc.
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+ This file is part of the GNU C Library.
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+ Contributed by Olaf Flebbe.
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+
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+ The GNU C Library is free software; you can redistribute it and/or
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+ modify it under the terms of the GNU Lesser General Public
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+ License as published by the Free Software Foundation; either
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+ version 2.1 of the License, or (at your option) any later version.
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+
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+ The GNU C Library is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ Lesser General Public License for more details.
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+
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+ You should have received a copy of the GNU Lesser General Public
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+ License along with the GNU C Library; if not, see
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+ <http://www.gnu.org/licenses/>. */
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+
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+#ifndef _FPU_CONTROL_H
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+#define _FPU_CONTROL_H 1
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+
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+/* Note that this file sets on x86-64 only the x87 FPU, it does not
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+ touch the SSE unit. */
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+
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+/* Here is the dirty part. Set up your 387 through the control word
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+ * (cw) register.
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+ *
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+ * 15-13 12 11-10 9-8 7-6 5 4 3 2 1 0
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+ * | reserved | IC | RC | PC | reserved | PM | UM | OM | ZM | DM | IM
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+ *
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+ * IM: Invalid operation mask
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+ * DM: Denormalized operand mask
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+ * ZM: Zero-divide mask
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+ * OM: Overflow mask
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+ * UM: Underflow mask
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+ * PM: Precision (inexact result) mask
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+ *
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+ * Mask bit is 1 means no interrupt.
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+ *
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+ * PC: Precision control
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+ * 11 - round to extended precision
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+ * 10 - round to double precision
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+ * 00 - round to single precision
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+ *
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+ * RC: Rounding control
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+ * 00 - rounding to nearest
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+ * 01 - rounding down (toward - infinity)
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+ * 10 - rounding up (toward + infinity)
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+ * 11 - rounding toward zero
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+ *
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+ * IC: Infinity control
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+ * That is for 8087 and 80287 only.
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+ *
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+ * The hardware default is 0x037f which we use.
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+ */
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+
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+#include <features.h>
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+
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+/* masking of interrupts */
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+#define _FPU_MASK_IM 0x01
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+#define _FPU_MASK_DM 0x02
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+#define _FPU_MASK_ZM 0x04
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+#define _FPU_MASK_OM 0x08
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+#define _FPU_MASK_UM 0x10
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+#define _FPU_MASK_PM 0x20
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+
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+/* precision control */
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+#define _FPU_EXTENDED 0x300 /* libm requires double extended precision. */
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+#define _FPU_DOUBLE 0x200
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+#define _FPU_SINGLE 0x0
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+
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+/* rounding control */
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+#define _FPU_RC_NEAREST 0x0 /* RECOMMENDED */
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+#define _FPU_RC_DOWN 0x400
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+#define _FPU_RC_UP 0x800
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+#define _FPU_RC_ZERO 0xC00
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+
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+#define _FPU_RESERVED 0xF0C0 /* Reserved bits in cw */
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+
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+
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+/* The fdlibm code requires strict IEEE double precision arithmetic,
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+ and no interrupts for exceptions, rounding to nearest. */
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+
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+#define _FPU_DEFAULT 0x037f
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+
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+/* IEEE: same as above. */
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+#define _FPU_IEEE 0x037f
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+
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+/* Type of the control word. */
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+typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__HI__)));
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+
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+/* Macros for accessing the hardware control word. "*&" is used to
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+ work around a bug in older versions of GCC. __volatile__ is used
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+ to support combination of writing the control register and reading
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+ it back. Without __volatile__, the old value may be used for reading
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+ back under compiler optimization.
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+
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+ Note that the use of these macros is not sufficient anymore with
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+ recent hardware nor on x86-64. Some floating point operations are
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+ executed in the SSE/SSE2 engines which have their own control and
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+ status register. */
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+#define _FPU_GETCW(cw) __asm__ __volatile__ ("fnstcw %0" : "=m" (*&cw))
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+#define _FPU_SETCW(cw) __asm__ __volatile__ ("fldcw %0" : : "m" (*&cw))
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+
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+/* Default control word set at startup. */
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+extern fpu_control_t __fpu_control;
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+
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+#endif /* fpu_control.h */
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+
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+#endif // AMD64
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+// ==============================================================================
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+// ==============================================================================
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+// ==============================================================================
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+
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address os::current_stack_pointer() {
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#ifdef SPARC_WORKS
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register void *esp;
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