This patch defines the correct optional Power ISA features that the
PPC code generator needs in order to run without crashing on v2.01
and older CPUs such as PPC 970 (G5) or NXP e6500, and to run more
efficiently on CPUs with features that weren't being used before.
PowerPC ISA v2.01 and older CPUs don't have FP round to int instructions,
and PowerPC ISA v2.06 and older are missing support for unsigned 64-bit
to/from double, as well as integer to/from single-precision float.
Use the current PPC_5_PLUS CPU feature to determine whether to generate
FP round to int, and use the PPC_7_PLUS feature to determine whether
to use the v2.06 ISA instructions or whether to generate an alternate
generic PPC sequence to handle the cases of 64-bit unsigned integer
to/from floating point, integers to single-precision floating point,
and loading and storing 64-bit integers with byte reversal.
Add a new PPC_7_PLUS_NXP feature for the popcnt and ldbrx/stdbrx
opcodes added in Power ISA v2.06, which are also present in the NXP
e5500 and e6500 cores, which are otherwise missing many of the
features added since v2.01. This enables NXP cores to use a few
more features. Additionally, bring back the ISELECT feature flag,
which is also supported by NXP cores, including older ones, and
has its own AT_HWCAP2 feature flag in Linux.
By defining a new ICACHE_SNOOP feature bit to replace the use of
PPC_6_PLUS, the meaning of the instruction cache flushing fast path,
and the CPUs that can use it, is more clearly defined. In addition,
for the other PowerPC chips, the loop to flush the data and instruction
cache blocks has been split into two loops, with a single "sync" and
"isync" after each loop, which should be more efficient, and also handles
the few CPUs with differing data and instruction cache line sizes.
In the macro assembler methods, in addition to providing an alternate
path for FP conversion opcodes added in POWER7 (ISA v2.06), unnecessary
instructions to move sp down and then immediately back up were replaced
with negative offsets from the current sp. This should be faster, and also
sp is supposed to point to a back chain at all times (V8 may not do this).
Closes https://github.com/void-ppc/void-packages/pull/62
This patch defines the correct optional Power ISA features that the
PPC code generator needs in order to run without crashing on v2.01
and older CPUs such as PPC 970 (G5) or NXP e6500, and to run more
efficiently on CPUs with features that weren't being used before.
PowerPC ISA v2.01 and older CPUs don't have FP round to int instructions,
and PowerPC ISA v2.06 and older are missing support for unsigned 64-bit
to/from double, as well as integer to/from single-precision float.
Add a new FP_ROUND_TO_INT CPU feature to determine whether to generate
FP round to int, and add a new PPC_7_PLUS feature to determine whether
to use the v2.06 FPR conversion instructions or generate an alternate
sequence to handle large 64-bit unsigned ints, and single-precision
using the v2.01 instructions with handling for large uint64_t values
as well as rounding results from double to single-precision.
Also add a new POP_COUNT feature for the popcnt opcodes added in v2.06,
which are also present in the NXP e5500 and e6500 cores, which are
otherwise missing many of the features added since v2.01.
By defining an ICACHE_SNOOP feature bit to replace the poorly-named
"LWSYNC", the meaning of the instruction cache flushing fast path,
and the CPUs that can use it, are more clearly defined. In addition,
for the other PowerPC chips, the loop to flush the data and instruction
cache blocks has been split into two loops, with a single "sync" and
"isync" after each loop, which should be more efficient, and also handles
the few CPUs with differing data and instruction cache line sizes.
In the macro assembler methods, in addition to providing an alternate
path for FP conversion opcodes added in POWER7 (ISA v2.06), unnecessary
instructions to move sp down and then immediately back up were replaced
with negative offsets from the current sp. This should be faster, and also
sp is supposed to point to a back chain at all times (V8 may not do this).
This patch also fixes ppc64 big-endian ELFv1 builds (not needed for Void).
Closes https://github.com/void-ppc/void-packages/pull/61
tibequadorian
Daniel Eyßer
Andrew J. Hesford
Andrew Benson
Leah Neukirchen
Michal Vasilek
Marcin Puc
Alex Lohr
Đoàn Trần Công Danh
bugcrazy
Arjan Mossel
classabbyamp
cinerea0
q66
Jake Hamby
mobinmob
Joel Beckmeyer