From b38bf2100cefe2f3b2d91892567830df680eac71 Mon Sep 17 00:00:00 2001
From: Christian Neukirchen <chneukirchen@gmail.com>
Date: Tue, 24 Nov 2015 14:52:39 +0100
Subject: [PATCH] libunwind: mips patches.

---
 common/shlibs                                 |  1 +
 srcpkgs/libunwind/patches/mips-musl.patch     | 11 +++
 .../libunwind/patches/mips-registers.patch    | 73 +++++++++++++++++++
 3 files changed, 85 insertions(+)
 create mode 100644 srcpkgs/libunwind/patches/mips-musl.patch
 create mode 100644 srcpkgs/libunwind/patches/mips-registers.patch

diff --git a/common/shlibs b/common/shlibs
index d8c397ec7ea..07ba1aba289 100644
--- a/common/shlibs
+++ b/common/shlibs
@@ -1226,6 +1226,7 @@ libunwind-ptrace.so.0 libunwind-1.1_1
 libunwind-x86_64.so.8 libunwind-1.1_1
 libunwind-x86.so.8 libunwind-1.1_1
 libunwind-arm.so.8 libunwind-1.1_4
+libunwind-mips.so.8 libunwind-1.1_4
 libmicrohttpd.so.10 libmicrohttpd-0.9.26_1
 libgit2.so.23 libgit2-0.23.1_1
 libgit2-glib-1.0.so.0 libgit2-glib-0.23.4_1
diff --git a/srcpkgs/libunwind/patches/mips-musl.patch b/srcpkgs/libunwind/patches/mips-musl.patch
new file mode 100644
index 00000000000..b2bd99e78e8
--- /dev/null
+++ b/srcpkgs/libunwind/patches/mips-musl.patch
@@ -0,0 +1,11 @@
+--- src/mips/getcontext.S.orig
++++ src/mips/getcontext.S
+@@ -24,7 +24,7 @@
+ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+ 
+ #include "offsets.h"
+-#include <endian.h>
++#include <bits/endian.h>
+ 
+ 	.text
+ 
diff --git a/srcpkgs/libunwind/patches/mips-registers.patch b/srcpkgs/libunwind/patches/mips-registers.patch
new file mode 100644
index 00000000000..8ed549f2ce1
--- /dev/null
+++ b/srcpkgs/libunwind/patches/mips-registers.patch
@@ -0,0 +1,73 @@
+Hardcoded according to _MIPS_SIM _ABIO32 (-mabi=32)!
+
+--- src/coredump/_UCD_access_reg_linux.c.orig
++++ src/coredump/_UCD_access_reg_linux.c
+@@ -49,37 +49,37 @@
+ #if defined(UNW_TARGET_MIPS)
+   static const uint8_t remap_regs[] =
+     {
+-      [UNW_MIPS_R0]  = EF_REG0,
+-      [UNW_MIPS_R1]  = EF_REG1,
+-      [UNW_MIPS_R2]  = EF_REG2,
+-      [UNW_MIPS_R3]  = EF_REG3,
+-      [UNW_MIPS_R4]  = EF_REG4,
+-      [UNW_MIPS_R5]  = EF_REG5,
+-      [UNW_MIPS_R6]  = EF_REG6,
+-      [UNW_MIPS_R7]  = EF_REG7,
+-      [UNW_MIPS_R8]  = EF_REG8,
+-      [UNW_MIPS_R9]  = EF_REG9,
+-      [UNW_MIPS_R10] = EF_REG10,
+-      [UNW_MIPS_R11] = EF_REG11,
+-      [UNW_MIPS_R12] = EF_REG12,
+-      [UNW_MIPS_R13] = EF_REG13,
+-      [UNW_MIPS_R14] = EF_REG14,
+-      [UNW_MIPS_R15] = EF_REG15,
+-      [UNW_MIPS_R16] = EF_REG16,
+-      [UNW_MIPS_R17] = EF_REG17,
+-      [UNW_MIPS_R18] = EF_REG18,
+-      [UNW_MIPS_R19] = EF_REG19,
+-      [UNW_MIPS_R20] = EF_REG20,
+-      [UNW_MIPS_R21] = EF_REG21,
+-      [UNW_MIPS_R22] = EF_REG22,
+-      [UNW_MIPS_R23] = EF_REG23,
+-      [UNW_MIPS_R24] = EF_REG24,
+-      [UNW_MIPS_R25] = EF_REG25,
+-      [UNW_MIPS_R28] = EF_REG28,
+-      [UNW_MIPS_R29] = EF_REG29,
+-      [UNW_MIPS_R30] = EF_REG30,
+-      [UNW_MIPS_R31] = EF_REG31,
+-      [UNW_MIPS_PC]  = EF_CP0_EPC,
++      [UNW_MIPS_R0]  = 6,
++      [UNW_MIPS_R1]  = 7,
++      [UNW_MIPS_R2]  = 8,
++      [UNW_MIPS_R3]  = 9,
++      [UNW_MIPS_R4]  = 10,
++      [UNW_MIPS_R5]  = 11,
++      [UNW_MIPS_R6]  = 12,
++      [UNW_MIPS_R7]  = 13,
++      [UNW_MIPS_R8]  = 14,
++      [UNW_MIPS_R9]  = 15,
++      [UNW_MIPS_R10] = 16,
++      [UNW_MIPS_R11] = 17,
++      [UNW_MIPS_R12] = 18,
++      [UNW_MIPS_R13] = 19,
++      [UNW_MIPS_R14] = 20,
++      [UNW_MIPS_R15] = 21,
++      [UNW_MIPS_R16] = 22,
++      [UNW_MIPS_R17] = 23,
++      [UNW_MIPS_R18] = 24,
++      [UNW_MIPS_R19] = 25,
++      [UNW_MIPS_R20] = 26,
++      [UNW_MIPS_R21] = 27,
++      [UNW_MIPS_R22] = 28,
++      [UNW_MIPS_R23] = 29,
++      [UNW_MIPS_R24] = 30,
++      [UNW_MIPS_R25] = 31,
++      [UNW_MIPS_R28] = 34,
++      [UNW_MIPS_R29] = 35,
++      [UNW_MIPS_R30] = 36,
++      [UNW_MIPS_R31] = 37,
++      [UNW_MIPS_PC]  = 40,
+     };
+ #elif defined(UNW_TARGET_X86)
+   static const uint8_t remap_regs[] =