void-packages/srcpkgs/ispc/patches/llvm12-009.patch

From 97b13c32132e2704a5e3e7b2eae49d854d087e3e Mon Sep 17 00:00:00 2001
From: Arina Neshlyaeva <arina.neshlyaeva@intel.com>
Date: Tue, 4 May 2021 11:31:55 -0700
Subject: [PATCH] Updated builtins-cm* for switch to LLVM12

---
 builtins/builtins-cm-32.ll | 234 ++++++++++++++++++-------------------
 builtins/builtins-cm-64.ll | 232 ++++++++++++++++++------------------
 2 files changed, 233 insertions(+), 233 deletions(-)

diff --git a/builtins/builtins-cm-32.ll b/builtins/builtins-cm-32.ll
index 32debf32e..481bbdc48 100644
--- a/builtins/builtins-cm-32.ll
+++ b/builtins/builtins-cm-32.ll
@@ -557,7 +557,7 @@ $_ZN13VaryingWriter12WriteVecElemIPvEEvv = comdat any
 @.str.10 = private unnamed_addr constant [5 x i8] c"%08X\00", align 1
 
 ; Function Attrs: noinline nounwind
-define dso_local signext i8 @_Z24__cm_intrinsic_impl_sdivcc(i8 signext, i8 signext) #0 {
+define internal signext i8 @_Z24__cm_intrinsic_impl_sdivcc(i8 signext, i8 signext) #0 {
   %3 = alloca i8, align 1
   %4 = alloca i8, align 1
   %5 = alloca <1 x i8>, align 1
@@ -618,7 +618,7 @@ define internal <1 x i8> @_ZN7details13__impl_divremILi1EEEu2CMvbT__cS1_S1_u2CMv
 declare <1 x i8> @llvm.genx.rdregioni.v1i8.v1i8.i16(<1 x i8>, i32, i32, i32, i16, i32) #2
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i8> @_Z24__cm_intrinsic_impl_sdivu2CMvb1_cS_(<1 x i8>, <1 x i8>) #0 {
+define internal <1 x i8> @_Z24__cm_intrinsic_impl_sdivu2CMvb1_cS_(<1 x i8>, <1 x i8>) #0 {
   %3 = alloca <1 x i8>, align 1
   %4 = alloca <1 x i8>, align 1
   %5 = alloca <1 x i8>, align 1
@@ -634,7 +634,7 @@ define dso_local <1 x i8> @_Z24__cm_intrinsic_impl_sdivu2CMvb1_cS_(<1 x i8>, <1
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i8> @_Z24__cm_intrinsic_impl_sdivu2CMvb2_cS_(<2 x i8>, <2 x i8>) #3 {
+define internal <2 x i8> @_Z24__cm_intrinsic_impl_sdivu2CMvb2_cS_(<2 x i8>, <2 x i8>) #3 {
   %3 = alloca <2 x i8>, align 2
   %4 = alloca <2 x i8>, align 2
   %5 = alloca <2 x i8>, align 2
@@ -680,7 +680,7 @@ define internal <2 x i8> @_ZN7details13__impl_divremILi2EEEu2CMvbT__cS1_S1_u2CMv
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i8> @_Z24__cm_intrinsic_impl_sdivu2CMvb4_cS_(<4 x i8>, <4 x i8>) #5 {
+define internal <4 x i8> @_Z24__cm_intrinsic_impl_sdivu2CMvb4_cS_(<4 x i8>, <4 x i8>) #5 {
   %3 = alloca <4 x i8>, align 4
   %4 = alloca <4 x i8>, align 4
   %5 = alloca <4 x i8>, align 4
@@ -818,7 +818,7 @@ define internal <16 x i8> @_ZN7details13__impl_divremILi16EEEu2CMvbT__cS1_S1_u2C
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i8> @_Z24__cm_intrinsic_impl_sdivu2CMvb32_cS_(<32 x i8>, <32 x i8>) #11 {
+define internal <32 x i8> @_Z24__cm_intrinsic_impl_sdivu2CMvb32_cS_(<32 x i8>, <32 x i8>) #11 {
   %3 = alloca <32 x i8>, align 32
   %4 = alloca <32 x i8>, align 32
   %5 = alloca <32 x i8>, align 32
@@ -864,7 +864,7 @@ define internal <32 x i8> @_ZN7details13__impl_divremILi32EEEu2CMvbT__cS1_S1_u2C
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local signext i8 @_Z24__cm_intrinsic_impl_sremcc(i8 signext, i8 signext) #0 {
+define internal signext i8 @_Z24__cm_intrinsic_impl_sremcc(i8 signext, i8 signext) #0 {
   %3 = alloca i8, align 1
   %4 = alloca i8, align 1
   %5 = alloca <1 x i8>, align 1
@@ -890,7 +890,7 @@ define dso_local signext i8 @_Z24__cm_intrinsic_impl_sremcc(i8 signext, i8 signe
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb1_cS_(<1 x i8>, <1 x i8>) #0 {
+define internal <1 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb1_cS_(<1 x i8>, <1 x i8>) #0 {
   %3 = alloca <1 x i8>, align 1
   %4 = alloca <1 x i8>, align 1
   %5 = alloca <1 x i8>, align 1
@@ -904,7 +904,7 @@ define dso_local <1 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb1_cS_(<1 x i8>, <1
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb2_cS_(<2 x i8>, <2 x i8>) #3 {
+define internal <2 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb2_cS_(<2 x i8>, <2 x i8>) #3 {
   %3 = alloca <2 x i8>, align 2
   %4 = alloca <2 x i8>, align 2
   %5 = alloca <2 x i8>, align 2
@@ -918,7 +918,7 @@ define dso_local <2 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb2_cS_(<2 x i8>, <2
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb4_cS_(<4 x i8>, <4 x i8>) #5 {
+define internal <4 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb4_cS_(<4 x i8>, <4 x i8>) #5 {
   %3 = alloca <4 x i8>, align 4
   %4 = alloca <4 x i8>, align 4
   %5 = alloca <4 x i8>, align 4
@@ -932,7 +932,7 @@ define dso_local <4 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb4_cS_(<4 x i8>, <4
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <8 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb8_cS_(<8 x i8>, <8 x i8>) #7 {
+define internal <8 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb8_cS_(<8 x i8>, <8 x i8>) #7 {
   %3 = alloca <8 x i8>, align 8
   %4 = alloca <8 x i8>, align 8
   %5 = alloca <8 x i8>, align 8
@@ -946,7 +946,7 @@ define dso_local <8 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb8_cS_(<8 x i8>, <8
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <16 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb16_cS_(<16 x i8>, <16 x i8>) #9 {
+define internal <16 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb16_cS_(<16 x i8>, <16 x i8>) #9 {
   %3 = alloca <16 x i8>, align 16
   %4 = alloca <16 x i8>, align 16
   %5 = alloca <16 x i8>, align 16
@@ -960,7 +960,7 @@ define dso_local <16 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb16_cS_(<16 x i8>,
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb32_cS_(<32 x i8>, <32 x i8>) #11 {
+define internal <32 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb32_cS_(<32 x i8>, <32 x i8>) #11 {
   %3 = alloca <32 x i8>, align 32
   %4 = alloca <32 x i8>, align 32
   %5 = alloca <32 x i8>, align 32
@@ -974,7 +974,7 @@ define dso_local <32 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb32_cS_(<32 x i8>,
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local signext i16 @_Z24__cm_intrinsic_impl_sdivss(i16 signext, i16 signext) #3 {
+define internal signext i16 @_Z24__cm_intrinsic_impl_sdivss(i16 signext, i16 signext) #3 {
   %3 = alloca i16, align 2
   %4 = alloca i16, align 2
   %5 = alloca <1 x i16>, align 2
@@ -1058,7 +1058,7 @@ define internal <1 x i16> @_ZN7details13__impl_divremILi1EEEu2CMvbT__sS1_S1_u2CM
 declare <1 x i16> @llvm.genx.rdregioni.v1i16.v1i16.i16(<1 x i16>, i32, i32, i32, i16, i32) #2
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i16> @_Z24__cm_intrinsic_impl_sdivu2CMvb1_sS_(<1 x i16>, <1 x i16>) #3 {
+define internal <1 x i16> @_Z24__cm_intrinsic_impl_sdivu2CMvb1_sS_(<1 x i16>, <1 x i16>) #3 {
   %3 = alloca <1 x i16>, align 2
   %4 = alloca <1 x i16>, align 2
   %5 = alloca <1 x i16>, align 2
@@ -1074,7 +1074,7 @@ define dso_local <1 x i16> @_Z24__cm_intrinsic_impl_sdivu2CMvb1_sS_(<1 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i16> @_Z24__cm_intrinsic_impl_sdivu2CMvb2_sS_(<2 x i16>, <2 x i16>) #5 {
+define internal <2 x i16> @_Z24__cm_intrinsic_impl_sdivu2CMvb2_sS_(<2 x i16>, <2 x i16>) #5 {
   %3 = alloca <2 x i16>, align 4
   %4 = alloca <2 x i16>, align 4
   %5 = alloca <2 x i16>, align 4
@@ -1143,7 +1143,7 @@ define internal <2 x i16> @_ZN7details13__impl_divremILi2EEEu2CMvbT__sS1_S1_u2CM
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i16> @_Z24__cm_intrinsic_impl_sdivu2CMvb4_sS_(<4 x i16>, <4 x i16>) #7 {
+define internal <4 x i16> @_Z24__cm_intrinsic_impl_sdivu2CMvb4_sS_(<4 x i16>, <4 x i16>) #7 {
   %3 = alloca <4 x i16>, align 8
   %4 = alloca <4 x i16>, align 8
   %5 = alloca <4 x i16>, align 8
@@ -1350,7 +1350,7 @@ define internal <16 x i16> @_ZN7details13__impl_divremILi16EEEu2CMvbT__sS1_S1_u2
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i16> @_Z24__cm_intrinsic_impl_sdivu2CMvb32_sS_(<32 x i16>, <32 x i16>) #13 {
+define internal <32 x i16> @_Z24__cm_intrinsic_impl_sdivu2CMvb32_sS_(<32 x i16>, <32 x i16>) #13 {
   %3 = alloca <32 x i16>, align 64
   %4 = alloca <32 x i16>, align 64
   %5 = alloca <32 x i16>, align 64
@@ -1419,7 +1419,7 @@ define internal <32 x i16> @_ZN7details13__impl_divremILi32EEEu2CMvbT__sS1_S1_u2
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local signext i16 @_Z24__cm_intrinsic_impl_sremss(i16 signext, i16 signext) #3 {
+define internal signext i16 @_Z24__cm_intrinsic_impl_sremss(i16 signext, i16 signext) #3 {
   %3 = alloca i16, align 2
   %4 = alloca i16, align 2
   %5 = alloca <1 x i16>, align 2
@@ -1445,7 +1445,7 @@ define dso_local signext i16 @_Z24__cm_intrinsic_impl_sremss(i16 signext, i16 si
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb1_sS_(<1 x i16>, <1 x i16>) #3 {
+define internal <1 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb1_sS_(<1 x i16>, <1 x i16>) #3 {
   %3 = alloca <1 x i16>, align 2
   %4 = alloca <1 x i16>, align 2
   %5 = alloca <1 x i16>, align 2
@@ -1459,7 +1459,7 @@ define dso_local <1 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb1_sS_(<1 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb2_sS_(<2 x i16>, <2 x i16>) #5 {
+define internal <2 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb2_sS_(<2 x i16>, <2 x i16>) #5 {
   %3 = alloca <2 x i16>, align 4
   %4 = alloca <2 x i16>, align 4
   %5 = alloca <2 x i16>, align 4
@@ -1473,7 +1473,7 @@ define dso_local <2 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb2_sS_(<2 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb4_sS_(<4 x i16>, <4 x i16>) #7 {
+define internal <4 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb4_sS_(<4 x i16>, <4 x i16>) #7 {
   %3 = alloca <4 x i16>, align 8
   %4 = alloca <4 x i16>, align 8
   %5 = alloca <4 x i16>, align 8
@@ -1487,7 +1487,7 @@ define dso_local <4 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb4_sS_(<4 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <8 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb8_sS_(<8 x i16>, <8 x i16>) #9 {
+define internal <8 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb8_sS_(<8 x i16>, <8 x i16>) #9 {
   %3 = alloca <8 x i16>, align 16
   %4 = alloca <8 x i16>, align 16
   %5 = alloca <8 x i16>, align 16
@@ -1501,7 +1501,7 @@ define dso_local <8 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb8_sS_(<8 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <16 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb16_sS_(<16 x i16>, <16 x i16>) #11 {
+define internal <16 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb16_sS_(<16 x i16>, <16 x i16>) #11 {
   %3 = alloca <16 x i16>, align 32
   %4 = alloca <16 x i16>, align 32
   %5 = alloca <16 x i16>, align 32
@@ -1515,7 +1515,7 @@ define dso_local <16 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb16_sS_(<16 x i16>
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb32_sS_(<32 x i16>, <32 x i16>) #13 {
+define internal <32 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb32_sS_(<32 x i16>, <32 x i16>) #13 {
   %3 = alloca <32 x i16>, align 64
   %4 = alloca <32 x i16>, align 64
   %5 = alloca <32 x i16>, align 64
@@ -1529,7 +1529,7 @@ define dso_local <32 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb32_sS_(<32 x i16>
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local i32 @_Z24__cm_intrinsic_impl_sdivii(i32, i32) #14 {
+define internal i32 @_Z24__cm_intrinsic_impl_sdivii(i32, i32) #14 {
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
   %5 = alloca <1 x i32>, align 4
@@ -1730,7 +1730,7 @@ define internal <1 x i32> @_ZN7details13__impl_divremILi1EEEu2CMvbT__iS1_S1_u2CM
 declare <1 x i32> @llvm.genx.rdregioni.v1i32.v1i32.i16(<1 x i32>, i32, i32, i32, i16, i32) #2
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i32> @_Z24__cm_intrinsic_impl_sdivu2CMvb1_iS_(<1 x i32>, <1 x i32>) #14 {
+define internal <1 x i32> @_Z24__cm_intrinsic_impl_sdivu2CMvb1_iS_(<1 x i32>, <1 x i32>) #14 {
   %3 = alloca <1 x i32>, align 4
   %4 = alloca <1 x i32>, align 4
   %5 = alloca <1 x i32>, align 4
@@ -1746,7 +1746,7 @@ define dso_local <1 x i32> @_Z24__cm_intrinsic_impl_sdivu2CMvb1_iS_(<1 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i32> @_Z24__cm_intrinsic_impl_sdivu2CMvb2_iS_(<2 x i32>, <2 x i32>) #15 {
+define internal <2 x i32> @_Z24__cm_intrinsic_impl_sdivu2CMvb2_iS_(<2 x i32>, <2 x i32>) #15 {
   %3 = alloca <2 x i32>, align 8
   %4 = alloca <2 x i32>, align 8
   %5 = alloca <2 x i32>, align 8
@@ -1932,7 +1932,7 @@ define internal <2 x i32> @_ZN7details13__impl_divremILi2EEEu2CMvbT__iS1_S1_u2CM
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i32> @_Z24__cm_intrinsic_impl_sdivu2CMvb4_iS_(<4 x i32>, <4 x i32>) #16 {
+define internal <4 x i32> @_Z24__cm_intrinsic_impl_sdivu2CMvb4_iS_(<4 x i32>, <4 x i32>) #16 {
   %3 = alloca <4 x i32>, align 16
   %4 = alloca <4 x i32>, align 16
   %5 = alloca <4 x i32>, align 16
@@ -2490,7 +2490,7 @@ define internal <16 x i32> @_ZN7details13__impl_divremILi16EEEu2CMvbT__iS1_S1_u2
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i32> @_Z24__cm_intrinsic_impl_sdivu2CMvb32_iS_(<32 x i32>, <32 x i32>) #19 {
+define internal <32 x i32> @_Z24__cm_intrinsic_impl_sdivu2CMvb32_iS_(<32 x i32>, <32 x i32>) #19 {
   %3 = alloca <32 x i32>, align 128
   %4 = alloca <32 x i32>, align 128
   %5 = alloca <32 x i32>, align 128
@@ -2676,7 +2676,7 @@ define internal <32 x i32> @_ZN7details13__impl_divremILi32EEEu2CMvbT__iS1_S1_u2
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local i32 @_Z24__cm_intrinsic_impl_sremii(i32, i32) #14 {
+define internal i32 @_Z24__cm_intrinsic_impl_sremii(i32, i32) #14 {
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
   %5 = alloca <1 x i32>, align 4
@@ -2702,7 +2702,7 @@ define dso_local i32 @_Z24__cm_intrinsic_impl_sremii(i32, i32) #14 {
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb1_iS_(<1 x i32>, <1 x i32>) #14 {
+define internal <1 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb1_iS_(<1 x i32>, <1 x i32>) #14 {
   %3 = alloca <1 x i32>, align 4
   %4 = alloca <1 x i32>, align 4
   %5 = alloca <1 x i32>, align 4
@@ -2716,7 +2716,7 @@ define dso_local <1 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb1_iS_(<1 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb2_iS_(<2 x i32>, <2 x i32>) #15 {
+define internal <2 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb2_iS_(<2 x i32>, <2 x i32>) #15 {
   %3 = alloca <2 x i32>, align 8
   %4 = alloca <2 x i32>, align 8
   %5 = alloca <2 x i32>, align 8
@@ -2730,7 +2730,7 @@ define dso_local <2 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb2_iS_(<2 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb4_iS_(<4 x i32>, <4 x i32>) #16 {
+define internal <4 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb4_iS_(<4 x i32>, <4 x i32>) #16 {
   %3 = alloca <4 x i32>, align 16
   %4 = alloca <4 x i32>, align 16
   %5 = alloca <4 x i32>, align 16
@@ -2744,7 +2744,7 @@ define dso_local <4 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb4_iS_(<4 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <8 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb8_iS_(<8 x i32>, <8 x i32>) #17 {
+define internal <8 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb8_iS_(<8 x i32>, <8 x i32>) #17 {
   %3 = alloca <8 x i32>, align 32
   %4 = alloca <8 x i32>, align 32
   %5 = alloca <8 x i32>, align 32
@@ -2758,7 +2758,7 @@ define dso_local <8 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb8_iS_(<8 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <16 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb16_iS_(<16 x i32>, <16 x i32>) #18 {
+define internal <16 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb16_iS_(<16 x i32>, <16 x i32>) #18 {
   %3 = alloca <16 x i32>, align 64
   %4 = alloca <16 x i32>, align 64
   %5 = alloca <16 x i32>, align 64
@@ -2772,7 +2772,7 @@ define dso_local <16 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb16_iS_(<16 x i32>
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb32_iS_(<32 x i32>, <32 x i32>) #19 {
+define internal <32 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb32_iS_(<32 x i32>, <32 x i32>) #19 {
   %3 = alloca <32 x i32>, align 128
   %4 = alloca <32 x i32>, align 128
   %5 = alloca <32 x i32>, align 128
@@ -2786,7 +2786,7 @@ define dso_local <32 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb32_iS_(<32 x i32>
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local zeroext i8 @_Z24__cm_intrinsic_impl_udivhh(i8 zeroext, i8 zeroext) #21 {
+define internal zeroext i8 @_Z24__cm_intrinsic_impl_udivhh(i8 zeroext, i8 zeroext) #21 {
   %3 = alloca i8, align 1
   %4 = alloca i8, align 1
   %5 = alloca <1 x i8>, align 1
@@ -2844,7 +2844,7 @@ define internal <1 x i8> @_ZN7details14__impl_udivremILi1EEEu2CMvbT__hS1_S1_u2CM
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i8> @_Z24__cm_intrinsic_impl_udivu2CMvb1_hS_(<1 x i8>, <1 x i8>) #21 {
+define internal <1 x i8> @_Z24__cm_intrinsic_impl_udivu2CMvb1_hS_(<1 x i8>, <1 x i8>) #21 {
   %3 = alloca <1 x i8>, align 1
   %4 = alloca <1 x i8>, align 1
   %5 = alloca <1 x i8>, align 1
@@ -2860,7 +2860,7 @@ define dso_local <1 x i8> @_Z24__cm_intrinsic_impl_udivu2CMvb1_hS_(<1 x i8>, <1
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i8> @_Z24__cm_intrinsic_impl_udivu2CMvb2_hS_(<2 x i8>, <2 x i8>) #22 {
+define internal <2 x i8> @_Z24__cm_intrinsic_impl_udivu2CMvb2_hS_(<2 x i8>, <2 x i8>) #22 {
   %3 = alloca <2 x i8>, align 2
   %4 = alloca <2 x i8>, align 2
   %5 = alloca <2 x i8>, align 2
@@ -2906,7 +2906,7 @@ define internal <2 x i8> @_ZN7details14__impl_udivremILi2EEEu2CMvbT__hS1_S1_u2CM
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i8> @_Z24__cm_intrinsic_impl_udivu2CMvb4_hS_(<4 x i8>, <4 x i8>) #14 {
+define internal <4 x i8> @_Z24__cm_intrinsic_impl_udivu2CMvb4_hS_(<4 x i8>, <4 x i8>) #14 {
   %3 = alloca <4 x i8>, align 4
   %4 = alloca <4 x i8>, align 4
   %5 = alloca <4 x i8>, align 4
@@ -3044,7 +3044,7 @@ define internal <16 x i8> @_ZN7details14__impl_udivremILi16EEEu2CMvbT__hS1_S1_u2
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i8> @_Z24__cm_intrinsic_impl_udivu2CMvb32_hS_(<32 x i8>, <32 x i8>) #17 {
+define internal <32 x i8> @_Z24__cm_intrinsic_impl_udivu2CMvb32_hS_(<32 x i8>, <32 x i8>) #17 {
   %3 = alloca <32 x i8>, align 32
   %4 = alloca <32 x i8>, align 32
   %5 = alloca <32 x i8>, align 32
@@ -3090,7 +3090,7 @@ define internal <32 x i8> @_ZN7details14__impl_udivremILi32EEEu2CMvbT__hS1_S1_u2
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local zeroext i8 @_Z24__cm_intrinsic_impl_uremhh(i8 zeroext, i8 zeroext) #21 {
+define internal zeroext i8 @_Z24__cm_intrinsic_impl_uremhh(i8 zeroext, i8 zeroext) #21 {
   %3 = alloca i8, align 1
   %4 = alloca i8, align 1
   %5 = alloca <1 x i8>, align 1
@@ -3116,7 +3116,7 @@ define dso_local zeroext i8 @_Z24__cm_intrinsic_impl_uremhh(i8 zeroext, i8 zeroe
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb1_hS_(<1 x i8>, <1 x i8>) #21 {
+define internal <1 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb1_hS_(<1 x i8>, <1 x i8>) #21 {
   %3 = alloca <1 x i8>, align 1
   %4 = alloca <1 x i8>, align 1
   %5 = alloca <1 x i8>, align 1
@@ -3130,7 +3130,7 @@ define dso_local <1 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb1_hS_(<1 x i8>, <1
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb2_hS_(<2 x i8>, <2 x i8>) #22 {
+define internal <2 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb2_hS_(<2 x i8>, <2 x i8>) #22 {
   %3 = alloca <2 x i8>, align 2
   %4 = alloca <2 x i8>, align 2
   %5 = alloca <2 x i8>, align 2
@@ -3144,7 +3144,7 @@ define dso_local <2 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb2_hS_(<2 x i8>, <2
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb4_hS_(<4 x i8>, <4 x i8>) #14 {
+define internal <4 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb4_hS_(<4 x i8>, <4 x i8>) #14 {
   %3 = alloca <4 x i8>, align 4
   %4 = alloca <4 x i8>, align 4
   %5 = alloca <4 x i8>, align 4
@@ -3158,7 +3158,7 @@ define dso_local <4 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb4_hS_(<4 x i8>, <4
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <8 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb8_hS_(<8 x i8>, <8 x i8>) #15 {
+define internal <8 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb8_hS_(<8 x i8>, <8 x i8>) #15 {
   %3 = alloca <8 x i8>, align 8
   %4 = alloca <8 x i8>, align 8
   %5 = alloca <8 x i8>, align 8
@@ -3172,7 +3172,7 @@ define dso_local <8 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb8_hS_(<8 x i8>, <8
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <16 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb16_hS_(<16 x i8>, <16 x i8>) #16 {
+define internal <16 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb16_hS_(<16 x i8>, <16 x i8>) #16 {
   %3 = alloca <16 x i8>, align 16
   %4 = alloca <16 x i8>, align 16
   %5 = alloca <16 x i8>, align 16
@@ -3186,7 +3186,7 @@ define dso_local <16 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb16_hS_(<16 x i8>,
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb32_hS_(<32 x i8>, <32 x i8>) #17 {
+define internal <32 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb32_hS_(<32 x i8>, <32 x i8>) #17 {
   %3 = alloca <32 x i8>, align 32
   %4 = alloca <32 x i8>, align 32
   %5 = alloca <32 x i8>, align 32
@@ -3200,7 +3200,7 @@ define dso_local <32 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb32_hS_(<32 x i8>,
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local zeroext i16 @_Z24__cm_intrinsic_impl_udivtt(i16 zeroext, i16 zeroext) #22 {
+define internal zeroext i16 @_Z24__cm_intrinsic_impl_udivtt(i16 zeroext, i16 zeroext) #22 {
   %3 = alloca i16, align 2
   %4 = alloca i16, align 2
   %5 = alloca <1 x i16>, align 2
@@ -3278,7 +3278,7 @@ define internal <1 x i16> @_ZN7details14__impl_udivremILi1EEEu2CMvbT__tS1_S1_u2C
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i16> @_Z24__cm_intrinsic_impl_udivu2CMvb1_tS_(<1 x i16>, <1 x i16>) #22 {
+define internal <1 x i16> @_Z24__cm_intrinsic_impl_udivu2CMvb1_tS_(<1 x i16>, <1 x i16>) #22 {
   %3 = alloca <1 x i16>, align 2
   %4 = alloca <1 x i16>, align 2
   %5 = alloca <1 x i16>, align 2
@@ -3294,7 +3294,7 @@ define dso_local <1 x i16> @_Z24__cm_intrinsic_impl_udivu2CMvb1_tS_(<1 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i16> @_Z24__cm_intrinsic_impl_udivu2CMvb2_tS_(<2 x i16>, <2 x i16>) #14 {
+define internal <2 x i16> @_Z24__cm_intrinsic_impl_udivu2CMvb2_tS_(<2 x i16>, <2 x i16>) #14 {
   %3 = alloca <2 x i16>, align 4
   %4 = alloca <2 x i16>, align 4
   %5 = alloca <2 x i16>, align 4
@@ -3360,7 +3360,7 @@ define internal <2 x i16> @_ZN7details14__impl_udivremILi2EEEu2CMvbT__tS1_S1_u2C
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i16> @_Z24__cm_intrinsic_impl_udivu2CMvb4_tS_(<4 x i16>, <4 x i16>) #15 {
+define internal <4 x i16> @_Z24__cm_intrinsic_impl_udivu2CMvb4_tS_(<4 x i16>, <4 x i16>) #15 {
   %3 = alloca <4 x i16>, align 8
   %4 = alloca <4 x i16>, align 8
   %5 = alloca <4 x i16>, align 8
@@ -3558,7 +3558,7 @@ define internal <16 x i16> @_ZN7details14__impl_udivremILi16EEEu2CMvbT__tS1_S1_u
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i16> @_Z24__cm_intrinsic_impl_udivu2CMvb32_tS_(<32 x i16>, <32 x i16>) #18 {
+define internal <32 x i16> @_Z24__cm_intrinsic_impl_udivu2CMvb32_tS_(<32 x i16>, <32 x i16>) #18 {
   %3 = alloca <32 x i16>, align 64
   %4 = alloca <32 x i16>, align 64
   %5 = alloca <32 x i16>, align 64
@@ -3624,7 +3624,7 @@ define internal <32 x i16> @_ZN7details14__impl_udivremILi32EEEu2CMvbT__tS1_S1_u
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local zeroext i16 @_Z24__cm_intrinsic_impl_uremtt(i16 zeroext, i16 zeroext) #22 {
+define internal zeroext i16 @_Z24__cm_intrinsic_impl_uremtt(i16 zeroext, i16 zeroext) #22 {
   %3 = alloca i16, align 2
   %4 = alloca i16, align 2
   %5 = alloca <1 x i16>, align 2
@@ -3650,7 +3650,7 @@ define dso_local zeroext i16 @_Z24__cm_intrinsic_impl_uremtt(i16 zeroext, i16 ze
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb1_tS_(<1 x i16>, <1 x i16>) #22 {
+define internal <1 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb1_tS_(<1 x i16>, <1 x i16>) #22 {
   %3 = alloca <1 x i16>, align 2
   %4 = alloca <1 x i16>, align 2
   %5 = alloca <1 x i16>, align 2
@@ -3664,7 +3664,7 @@ define dso_local <1 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb1_tS_(<1 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb2_tS_(<2 x i16>, <2 x i16>) #14 {
+define internal <2 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb2_tS_(<2 x i16>, <2 x i16>) #14 {
   %3 = alloca <2 x i16>, align 4
   %4 = alloca <2 x i16>, align 4
   %5 = alloca <2 x i16>, align 4
@@ -3678,7 +3678,7 @@ define dso_local <2 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb2_tS_(<2 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb4_tS_(<4 x i16>, <4 x i16>) #15 {
+define internal <4 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb4_tS_(<4 x i16>, <4 x i16>) #15 {
   %3 = alloca <4 x i16>, align 8
   %4 = alloca <4 x i16>, align 8
   %5 = alloca <4 x i16>, align 8
@@ -3692,7 +3692,7 @@ define dso_local <4 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb4_tS_(<4 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <8 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb8_tS_(<8 x i16>, <8 x i16>) #16 {
+define internal <8 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb8_tS_(<8 x i16>, <8 x i16>) #16 {
   %3 = alloca <8 x i16>, align 16
   %4 = alloca <8 x i16>, align 16
   %5 = alloca <8 x i16>, align 16
@@ -3706,7 +3706,7 @@ define dso_local <8 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb8_tS_(<8 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <16 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb16_tS_(<16 x i16>, <16 x i16>) #17 {
+define internal <16 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb16_tS_(<16 x i16>, <16 x i16>) #17 {
   %3 = alloca <16 x i16>, align 32
   %4 = alloca <16 x i16>, align 32
   %5 = alloca <16 x i16>, align 32
@@ -3720,7 +3720,7 @@ define dso_local <16 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb16_tS_(<16 x i16>
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb32_tS_(<32 x i16>, <32 x i16>) #18 {
+define internal <32 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb32_tS_(<32 x i16>, <32 x i16>) #18 {
   %3 = alloca <32 x i16>, align 64
   %4 = alloca <32 x i16>, align 64
   %5 = alloca <32 x i16>, align 64
@@ -3734,7 +3734,7 @@ define dso_local <32 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb32_tS_(<32 x i16>
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local i32 @_Z24__cm_intrinsic_impl_udivjj(i32, i32) #14 {
+define internal i32 @_Z24__cm_intrinsic_impl_udivjj(i32, i32) #14 {
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
   %5 = alloca <1 x i32>, align 4
@@ -3892,7 +3892,7 @@ define internal <1 x i32> @_ZN7details14__impl_udivremILi1EEEu2CMvbT__jS1_S1_u2C
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i32> @_Z24__cm_intrinsic_impl_udivu2CMvb1_jS_(<1 x i32>, <1 x i32>) #14 {
+define internal <1 x i32> @_Z24__cm_intrinsic_impl_udivu2CMvb1_jS_(<1 x i32>, <1 x i32>) #14 {
   %3 = alloca <1 x i32>, align 4
   %4 = alloca <1 x i32>, align 4
   %5 = alloca <1 x i32>, align 4
@@ -3908,7 +3908,7 @@ define dso_local <1 x i32> @_Z24__cm_intrinsic_impl_udivu2CMvb1_jS_(<1 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i32> @_Z24__cm_intrinsic_impl_udivu2CMvb2_jS_(<2 x i32>, <2 x i32>) #15 {
+define internal <2 x i32> @_Z24__cm_intrinsic_impl_udivu2CMvb2_jS_(<2 x i32>, <2 x i32>) #15 {
   %3 = alloca <2 x i32>, align 8
   %4 = alloca <2 x i32>, align 8
   %5 = alloca <2 x i32>, align 8
@@ -4054,7 +4054,7 @@ define internal <2 x i32> @_ZN7details14__impl_udivremILi2EEEu2CMvbT__jS1_S1_u2C
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i32> @_Z24__cm_intrinsic_impl_udivu2CMvb4_jS_(<4 x i32>, <4 x i32>) #16 {
+define internal <4 x i32> @_Z24__cm_intrinsic_impl_udivu2CMvb4_jS_(<4 x i32>, <4 x i32>) #16 {
   %3 = alloca <4 x i32>, align 16
   %4 = alloca <4 x i32>, align 16
   %5 = alloca <4 x i32>, align 16
@@ -4492,7 +4492,7 @@ define internal <16 x i32> @_ZN7details14__impl_udivremILi16EEEu2CMvbT__jS1_S1_u
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i32> @_Z24__cm_intrinsic_impl_udivu2CMvb32_jS_(<32 x i32>, <32 x i32>) #19 {
+define internal <32 x i32> @_Z24__cm_intrinsic_impl_udivu2CMvb32_jS_(<32 x i32>, <32 x i32>) #19 {
   %3 = alloca <32 x i32>, align 128
   %4 = alloca <32 x i32>, align 128
   %5 = alloca <32 x i32>, align 128
@@ -4638,7 +4638,7 @@ define internal <32 x i32> @_ZN7details14__impl_udivremILi32EEEu2CMvbT__jS1_S1_u
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local i32 @_Z24__cm_intrinsic_impl_uremjj(i32, i32) #14 {
+define internal i32 @_Z24__cm_intrinsic_impl_uremjj(i32, i32) #14 {
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
   %5 = alloca <1 x i32>, align 4
@@ -4664,7 +4664,7 @@ define dso_local i32 @_Z24__cm_intrinsic_impl_uremjj(i32, i32) #14 {
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb1_jS_(<1 x i32>, <1 x i32>) #14 {
+define internal <1 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb1_jS_(<1 x i32>, <1 x i32>) #14 {
   %3 = alloca <1 x i32>, align 4
   %4 = alloca <1 x i32>, align 4
   %5 = alloca <1 x i32>, align 4
@@ -4678,7 +4678,7 @@ define dso_local <1 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb1_jS_(<1 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb2_jS_(<2 x i32>, <2 x i32>) #15 {
+define internal <2 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb2_jS_(<2 x i32>, <2 x i32>) #15 {
   %3 = alloca <2 x i32>, align 8
   %4 = alloca <2 x i32>, align 8
   %5 = alloca <2 x i32>, align 8
@@ -4692,7 +4692,7 @@ define dso_local <2 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb2_jS_(<2 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb4_jS_(<4 x i32>, <4 x i32>) #16 {
+define internal <4 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb4_jS_(<4 x i32>, <4 x i32>) #16 {
   %3 = alloca <4 x i32>, align 16
   %4 = alloca <4 x i32>, align 16
   %5 = alloca <4 x i32>, align 16
@@ -4706,7 +4706,7 @@ define dso_local <4 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb4_jS_(<4 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <8 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb8_jS_(<8 x i32>, <8 x i32>) #17 {
+define internal <8 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb8_jS_(<8 x i32>, <8 x i32>) #17 {
   %3 = alloca <8 x i32>, align 32
   %4 = alloca <8 x i32>, align 32
   %5 = alloca <8 x i32>, align 32
@@ -4720,7 +4720,7 @@ define dso_local <8 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb8_jS_(<8 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <16 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb16_jS_(<16 x i32>, <16 x i32>) #18 {
+define internal <16 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb16_jS_(<16 x i32>, <16 x i32>) #18 {
   %3 = alloca <16 x i32>, align 64
   %4 = alloca <16 x i32>, align 64
   %5 = alloca <16 x i32>, align 64
@@ -4734,7 +4734,7 @@ define dso_local <16 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb16_jS_(<16 x i32>
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb32_jS_(<32 x i32>, <32 x i32>) #19 {
+define internal <32 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb32_jS_(<32 x i32>, <32 x i32>) #19 {
   %3 = alloca <32 x i32>, align 128
   %4 = alloca <32 x i32>, align 128
   %5 = alloca <32 x i32>, align 128
@@ -4748,7 +4748,7 @@ define dso_local <32 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb32_jS_(<32 x i32>
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local void @__do_print_cm(i8*, i8*, i32, i64, i32*, i32, i32) #23 !dbg !15 {
+define internal void @__do_print_cm(i8*, i8*, i32, i64, i32*, i32, i32) #23 !dbg !15 {
   %8 = alloca i8*, align 4
   %9 = alloca i8*, align 4
   %10 = alloca i32, align 4
@@ -4988,7 +4988,7 @@ define internal void @_ZN7details16_cm_print_formatILi128EEEv15cm_surfaceindexju
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local void @__do_print_lz(i32, i8*, i32, i64, i32*, i32, i32, i32, i32) #26 !dbg !117 {
+define internal void @__do_print_lz(i32, i8*, i32, i64, i32*, i32, i32, i32, i32) #26 !dbg !117 {
   %10 = alloca i32, align 4
   %11 = alloca i8*, align 4
   %12 = alloca i32, align 4
@@ -5069,7 +5069,7 @@ define dso_local void @__do_print_lz(i32, i8*, i32, i64, i32*, i32, i32, i32, i3
   %67 = load i64, i64* %13, align 8, !dbg !159, !tbaa !19
   %68 = load <5 x i32>, <5 x i32>* %21, align 32, !dbg !160, !tbaa !7
   call void @_ZN13VaryingWriterC2ERjRPKjiyu2CMvb5_i(%class.VaryingWriter* %23, i32* dereferenceable(4) %19, i32** dereferenceable(4) %14, i32 %66, i64 %67, <5 x i32> %68), !dbg !161
-  %69 = call zeroext i1 @_ZN9PrintInfo14switchEncodingI13UniformWriter13VaryingWriterEEbNS_8EncodingET_T0_(i8 signext %62, %class.UniformWriter* byval align 32 %22, %class.VaryingWriter* byval align 32 %23), !dbg !162
+  %69 = call zeroext i1 @_ZN9PrintInfo14switchEncodingI13UniformWriter13VaryingWriterEEbNS_8EncodingET_T0_(i8 signext %62, %class.UniformWriter* byval(%class.UniformWriter) align 32 %22, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %23), !dbg !162
   br label %70, !dbg !163
 
 ; <label>:70:                                     ; preds = %60
@@ -5187,7 +5187,7 @@ define internal <5 x i32> @_Z17get_auxiliary_strv() #28 comdat !dbg !178 {
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo14switchEncodingI13UniformWriter13VaryingWriterEEbNS_8EncodingET_T0_(i8 signext, %class.UniformWriter* byval align 32, %class.VaryingWriter* byval align 32) #25 comdat !dbg !191 {
+define internal zeroext i1 @_ZN9PrintInfo14switchEncodingI13UniformWriter13VaryingWriterEEbNS_8EncodingET_T0_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %class.VaryingWriter* byval(%class.VaryingWriter) align 32) #25 comdat !dbg !191 {
   %4 = alloca i8, align 1
   %5 = alloca %class.UniformWriter, align 32
   %6 = alloca %class.VaryingWriter, align 32
@@ -5196,7 +5196,7 @@ define internal zeroext i1 @_ZN9PrintInfo14switchEncodingI13UniformWriter13Varyi
   %8 = bitcast %class.UniformWriter* %5 to i8*, !dbg !196
   %9 = bitcast %class.UniformWriter* %1 to i8*, !dbg !196
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %8, i8* align 32 %9, i32 64, i1 false), !dbg !196, !tbaa.struct !197
-  %10 = call zeroext i1 @_ZN9PrintInfo22switchEncoding4UniformI13UniformWriterEEbNS_8EncodingET_(i8 signext %7, %class.UniformWriter* byval align 32 %5), !dbg !198
+  %10 = call zeroext i1 @_ZN9PrintInfo22switchEncoding4UniformI13UniformWriterEEbNS_8EncodingET_(i8 signext %7, %class.UniformWriter* byval(%class.UniformWriter) align 32 %5), !dbg !198
   br i1 %10, label %16, label %11, !dbg !199
 
 ; <label>:11:                                     ; preds = %3
@@ -5204,7 +5204,7 @@ define internal zeroext i1 @_ZN9PrintInfo14switchEncodingI13UniformWriter13Varyi
   %13 = bitcast %class.VaryingWriter* %6 to i8*, !dbg !201
   %14 = bitcast %class.VaryingWriter* %2 to i8*, !dbg !201
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %13, i8* align 32 %14, i32 64, i1 false), !dbg !201, !tbaa.struct !197
-  %15 = call zeroext i1 @_ZN9PrintInfo22switchEncoding4VaryingI13VaryingWriterEEbNS_8EncodingET_(i8 signext %12, %class.VaryingWriter* byval align 32 %6), !dbg !202
+  %15 = call zeroext i1 @_ZN9PrintInfo22switchEncoding4VaryingI13VaryingWriterEEbNS_8EncodingET_(i8 signext %12, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %6), !dbg !202
   br label %16, !dbg !199
 
 ; <label>:16:                                     ; preds = %11, %3
@@ -5279,7 +5279,7 @@ define internal void @_ZN13VaryingWriterC2ERjRPKjiyu2CMvb5_i(%class.VaryingWrite
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local i32 @__num_cores() #29 !dbg !236 {
+define internal i32 @__num_cores() #29 !dbg !236 {
   ret i32 -1, !dbg !237
 }
 
@@ -8860,7 +8860,7 @@ declare dso_local void @_ZN7details37__cm_intrinsic_impl_svm_scatter_writeIiLi1E
 declare void @llvm.genx.svm.scatter.v1i1.v1i64.v1i32(<1 x i1>, i32, <1 x i64>, <1 x i32>) #27
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo22switchEncoding4UniformI13UniformWriterEEbNS_8EncodingET_(i8 signext, %class.UniformWriter* byval align 32) #25 comdat !dbg !1645 {
+define internal zeroext i1 @_ZN9PrintInfo22switchEncoding4UniformI13UniformWriterEEbNS_8EncodingET_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32) #25 comdat !dbg !1645 {
   %3 = alloca i8, align 1
   %4 = alloca %class.UniformWriter, align 32
   %5 = alloca %"struct.PrintInfo::Encoding4Uniform", align 1
@@ -8869,7 +8869,7 @@ define internal zeroext i1 @_ZN9PrintInfo22switchEncoding4UniformI13UniformWrite
   %7 = bitcast %class.UniformWriter* %4 to i8*, !dbg !1647
   %8 = bitcast %class.UniformWriter* %1 to i8*, !dbg !1647
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %7, i8* align 32 %8, i32 64, i1 false), !dbg !1647, !tbaa.struct !197
-  %9 = call zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET_T0_(i8 signext %6, %class.UniformWriter* byval align 32 %4, %"struct.PrintInfo::Encoding4Uniform"* byval align 1 %5), !dbg !1648
+  %9 = call zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET_T0_(i8 signext %6, %class.UniformWriter* byval(%class.UniformWriter) align 32 %4, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1 %5), !dbg !1648
   ret i1 %9, !dbg !1649
 }
 
@@ -8877,7 +8877,7 @@ define internal zeroext i1 @_ZN9PrintInfo22switchEncoding4UniformI13UniformWrite
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1) #32
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo22switchEncoding4VaryingI13VaryingWriterEEbNS_8EncodingET_(i8 signext, %class.VaryingWriter* byval align 32) #25 comdat !dbg !1650 {
+define internal zeroext i1 @_ZN9PrintInfo22switchEncoding4VaryingI13VaryingWriterEEbNS_8EncodingET_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32) #25 comdat !dbg !1650 {
   %3 = alloca i8, align 1
   %4 = alloca %class.VaryingWriter, align 32
   %5 = alloca %"struct.PrintInfo::Encoding4Varying", align 1
@@ -8886,12 +8886,12 @@ define internal zeroext i1 @_ZN9PrintInfo22switchEncoding4VaryingI13VaryingWrite
   %7 = bitcast %class.VaryingWriter* %4 to i8*, !dbg !1652
   %8 = bitcast %class.VaryingWriter* %1 to i8*, !dbg !1652
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %7, i8* align 32 %8, i32 64, i1 false), !dbg !1652, !tbaa.struct !197
-  %9 = call zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET_T0_(i8 signext %6, %class.VaryingWriter* byval align 32 %4, %"struct.PrintInfo::Encoding4Varying"* byval align 1 %5), !dbg !1653
+  %9 = call zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET_T0_(i8 signext %6, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %4, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1 %5), !dbg !1653
   ret i1 %9, !dbg !1654
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET_T0_(i8 signext, %class.UniformWriter* byval align 32, %"struct.PrintInfo::Encoding4Uniform"* byval align 1) #25 comdat !dbg !1655 {
+define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET_T0_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1) #25 comdat !dbg !1655 {
   %4 = alloca i8, align 1
   %5 = alloca %class.UniformWriter, align 32
   %6 = alloca %"struct.PrintInfo::Encoding4Uniform", align 1
@@ -8914,7 +8914,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriter
   %22 = bitcast %class.UniformWriter* %5 to i8*, !dbg !1657
   %23 = bitcast %class.UniformWriter* %1 to i8*, !dbg !1657
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %22, i8* align 32 %23, i32 64, i1 false), !dbg !1657, !tbaa.struct !197
-  %24 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %21, %class.UniformWriter* byval align 32 %5, %"struct.PrintInfo::Encoding4Uniform"* byval align 1 %6), !dbg !1658
+  %24 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %21, %class.UniformWriter* byval(%class.UniformWriter) align 32 %5, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1 %6), !dbg !1658
   br i1 %24, label %60, label %25, !dbg !1659
 
 ; <label>:25:                                     ; preds = %3
@@ -8922,7 +8922,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriter
   %27 = bitcast %class.UniformWriter* %7 to i8*, !dbg !1661
   %28 = bitcast %class.UniformWriter* %1 to i8*, !dbg !1661
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %27, i8* align 32 %28, i32 64, i1 false), !dbg !1661, !tbaa.struct !197
-  %29 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %26, %class.UniformWriter* byval align 32 %7, %"struct.PrintInfo::Encoding4Uniform"* byval align 1 %8), !dbg !1662
+  %29 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %26, %class.UniformWriter* byval(%class.UniformWriter) align 32 %7, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1 %8), !dbg !1662
   br i1 %29, label %60, label %30, !dbg !1663
 
 ; <label>:30:                                     ; preds = %25
@@ -8930,7 +8930,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriter
   %32 = bitcast %class.UniformWriter* %9 to i8*, !dbg !1665
   %33 = bitcast %class.UniformWriter* %1 to i8*, !dbg !1665
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %32, i8* align 32 %33, i32 64, i1 false), !dbg !1665, !tbaa.struct !197
-  %34 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %31, %class.UniformWriter* byval align 32 %9, %"struct.PrintInfo::Encoding4Uniform"* byval align 1 %10), !dbg !1666
+  %34 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %31, %class.UniformWriter* byval(%class.UniformWriter) align 32 %9, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1 %10), !dbg !1666
   br i1 %34, label %60, label %35, !dbg !1667
 
 ; <label>:35:                                     ; preds = %30
@@ -8938,7 +8938,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriter
   %37 = bitcast %class.UniformWriter* %11 to i8*, !dbg !1669
   %38 = bitcast %class.UniformWriter* %1 to i8*, !dbg !1669
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %37, i8* align 32 %38, i32 64, i1 false), !dbg !1669, !tbaa.struct !197
-  %39 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %36, %class.UniformWriter* byval align 32 %11, %"struct.PrintInfo::Encoding4Uniform"* byval align 1 %12), !dbg !1670
+  %39 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %36, %class.UniformWriter* byval(%class.UniformWriter) align 32 %11, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1 %12), !dbg !1670
   br i1 %39, label %60, label %40, !dbg !1671
 
 ; <label>:40:                                     ; preds = %35
@@ -8946,7 +8946,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriter
   %42 = bitcast %class.UniformWriter* %13 to i8*, !dbg !1673
   %43 = bitcast %class.UniformWriter* %1 to i8*, !dbg !1673
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %42, i8* align 32 %43, i32 64, i1 false), !dbg !1673, !tbaa.struct !197
-  %44 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %41, %class.UniformWriter* byval align 32 %13, %"struct.PrintInfo::Encoding4Uniform"* byval align 1 %14), !dbg !1674
+  %44 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %41, %class.UniformWriter* byval(%class.UniformWriter) align 32 %13, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1 %14), !dbg !1674
   br i1 %44, label %60, label %45, !dbg !1675
 
 ; <label>:45:                                     ; preds = %40
@@ -8954,7 +8954,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriter
   %47 = bitcast %class.UniformWriter* %15 to i8*, !dbg !1677
   %48 = bitcast %class.UniformWriter* %1 to i8*, !dbg !1677
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %47, i8* align 32 %48, i32 64, i1 false), !dbg !1677, !tbaa.struct !197
-  %49 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %46, %class.UniformWriter* byval align 32 %15, %"struct.PrintInfo::Encoding4Uniform"* byval align 1 %16), !dbg !1678
+  %49 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %46, %class.UniformWriter* byval(%class.UniformWriter) align 32 %15, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1 %16), !dbg !1678
   br i1 %49, label %60, label %50, !dbg !1679
 
 ; <label>:50:                                     ; preds = %45
@@ -8962,7 +8962,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriter
   %52 = bitcast %class.UniformWriter* %17 to i8*, !dbg !1681
   %53 = bitcast %class.UniformWriter* %1 to i8*, !dbg !1681
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %52, i8* align 32 %53, i32 64, i1 false), !dbg !1681, !tbaa.struct !197
-  %54 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %51, %class.UniformWriter* byval align 32 %17, %"struct.PrintInfo::Encoding4Uniform"* byval align 1 %18), !dbg !1682
+  %54 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %51, %class.UniformWriter* byval(%class.UniformWriter) align 32 %17, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1 %18), !dbg !1682
   br i1 %54, label %60, label %55, !dbg !1683
 
 ; <label>:55:                                     ; preds = %50
@@ -8970,7 +8970,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriter
   %57 = bitcast %class.UniformWriter* %19 to i8*, !dbg !1685
   %58 = bitcast %class.UniformWriter* %1 to i8*, !dbg !1685
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %57, i8* align 32 %58, i32 64, i1 false), !dbg !1685, !tbaa.struct !197
-  %59 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIPv13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %56, %class.UniformWriter* byval align 32 %19, %"struct.PrintInfo::Encoding4Uniform"* byval align 1 %20), !dbg !1686
+  %59 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIPv13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %56, %class.UniformWriter* byval(%class.UniformWriter) align 32 %19, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1 %20), !dbg !1686
   br label %60, !dbg !1683
 
 ; <label>:60:                                     ; preds = %55, %50, %45, %40, %35, %30, %25, %3
@@ -8979,7 +8979,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriter
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval align 32, %"struct.PrintInfo::Encoding4Uniform"* byval align 1) #25 comdat !dbg !1688 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1) #25 comdat !dbg !1688 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -9005,7 +9005,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13Unifo
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval align 32, %"struct.PrintInfo::Encoding4Uniform"* byval align 1) #25 comdat !dbg !1697 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1) #25 comdat !dbg !1697 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -9031,7 +9031,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13Unifo
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval align 32, %"struct.PrintInfo::Encoding4Uniform"* byval align 1) #25 comdat !dbg !1706 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1) #25 comdat !dbg !1706 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -9057,7 +9057,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13Unifo
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval align 32, %"struct.PrintInfo::Encoding4Uniform"* byval align 1) #25 comdat !dbg !1715 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1) #25 comdat !dbg !1715 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -9083,7 +9083,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13Unifo
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval align 32, %"struct.PrintInfo::Encoding4Uniform"* byval align 1) #25 comdat !dbg !1724 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1) #25 comdat !dbg !1724 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -9109,7 +9109,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13Unifo
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval align 32, %"struct.PrintInfo::Encoding4Uniform"* byval align 1) #25 comdat !dbg !1733 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1) #25 comdat !dbg !1733 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -9135,7 +9135,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13Unifo
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval align 32, %"struct.PrintInfo::Encoding4Uniform"* byval align 1) #25 comdat !dbg !1742 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1) #25 comdat !dbg !1742 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -9161,7 +9161,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13Unifo
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIPv13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval align 32, %"struct.PrintInfo::Encoding4Uniform"* byval align 1) #25 comdat !dbg !1751 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIPv13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1) #25 comdat !dbg !1751 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -9984,7 +9984,7 @@ define internal i32 @_ZN7details18_cm_print_type_oclIPvEENS_18SHADER_PRINTF_TYPE
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET_T0_(i8 signext, %class.VaryingWriter* byval align 32, %"struct.PrintInfo::Encoding4Varying"* byval align 1) #25 comdat !dbg !2055 {
+define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET_T0_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1) #25 comdat !dbg !2055 {
   %4 = alloca i8, align 1
   %5 = alloca %class.VaryingWriter, align 32
   %6 = alloca %"struct.PrintInfo::Encoding4Varying", align 1
@@ -10007,7 +10007,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriter
   %22 = bitcast %class.VaryingWriter* %5 to i8*, !dbg !2057
   %23 = bitcast %class.VaryingWriter* %1 to i8*, !dbg !2057
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %22, i8* align 32 %23, i32 64, i1 false), !dbg !2057, !tbaa.struct !197
-  %24 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %21, %class.VaryingWriter* byval align 32 %5, %"struct.PrintInfo::Encoding4Varying"* byval align 1 %6), !dbg !2058
+  %24 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %21, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %5, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1 %6), !dbg !2058
   br i1 %24, label %60, label %25, !dbg !2059
 
 ; <label>:25:                                     ; preds = %3
@@ -10015,7 +10015,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriter
   %27 = bitcast %class.VaryingWriter* %7 to i8*, !dbg !2061
   %28 = bitcast %class.VaryingWriter* %1 to i8*, !dbg !2061
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %27, i8* align 32 %28, i32 64, i1 false), !dbg !2061, !tbaa.struct !197
-  %29 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %26, %class.VaryingWriter* byval align 32 %7, %"struct.PrintInfo::Encoding4Varying"* byval align 1 %8), !dbg !2062
+  %29 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %26, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %7, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1 %8), !dbg !2062
   br i1 %29, label %60, label %30, !dbg !2063
 
 ; <label>:30:                                     ; preds = %25
@@ -10023,7 +10023,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriter
   %32 = bitcast %class.VaryingWriter* %9 to i8*, !dbg !2065
   %33 = bitcast %class.VaryingWriter* %1 to i8*, !dbg !2065
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %32, i8* align 32 %33, i32 64, i1 false), !dbg !2065, !tbaa.struct !197
-  %34 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %31, %class.VaryingWriter* byval align 32 %9, %"struct.PrintInfo::Encoding4Varying"* byval align 1 %10), !dbg !2066
+  %34 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %31, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %9, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1 %10), !dbg !2066
   br i1 %34, label %60, label %35, !dbg !2067
 
 ; <label>:35:                                     ; preds = %30
@@ -10031,7 +10031,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriter
   %37 = bitcast %class.VaryingWriter* %11 to i8*, !dbg !2069
   %38 = bitcast %class.VaryingWriter* %1 to i8*, !dbg !2069
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %37, i8* align 32 %38, i32 64, i1 false), !dbg !2069, !tbaa.struct !197
-  %39 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %36, %class.VaryingWriter* byval align 32 %11, %"struct.PrintInfo::Encoding4Varying"* byval align 1 %12), !dbg !2070
+  %39 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %36, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %11, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1 %12), !dbg !2070
   br i1 %39, label %60, label %40, !dbg !2071
 
 ; <label>:40:                                     ; preds = %35
@@ -10039,7 +10039,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriter
   %42 = bitcast %class.VaryingWriter* %13 to i8*, !dbg !2073
   %43 = bitcast %class.VaryingWriter* %1 to i8*, !dbg !2073
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %42, i8* align 32 %43, i32 64, i1 false), !dbg !2073, !tbaa.struct !197
-  %44 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %41, %class.VaryingWriter* byval align 32 %13, %"struct.PrintInfo::Encoding4Varying"* byval align 1 %14), !dbg !2074
+  %44 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %41, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %13, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1 %14), !dbg !2074
   br i1 %44, label %60, label %45, !dbg !2075
 
 ; <label>:45:                                     ; preds = %40
@@ -10047,7 +10047,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriter
   %47 = bitcast %class.VaryingWriter* %15 to i8*, !dbg !2077
   %48 = bitcast %class.VaryingWriter* %1 to i8*, !dbg !2077
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %47, i8* align 32 %48, i32 64, i1 false), !dbg !2077, !tbaa.struct !197
-  %49 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %46, %class.VaryingWriter* byval align 32 %15, %"struct.PrintInfo::Encoding4Varying"* byval align 1 %16), !dbg !2078
+  %49 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %46, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %15, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1 %16), !dbg !2078
   br i1 %49, label %60, label %50, !dbg !2079
 
 ; <label>:50:                                     ; preds = %45
@@ -10055,7 +10055,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriter
   %52 = bitcast %class.VaryingWriter* %17 to i8*, !dbg !2081
   %53 = bitcast %class.VaryingWriter* %1 to i8*, !dbg !2081
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %52, i8* align 32 %53, i32 64, i1 false), !dbg !2081, !tbaa.struct !197
-  %54 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %51, %class.VaryingWriter* byval align 32 %17, %"struct.PrintInfo::Encoding4Varying"* byval align 1 %18), !dbg !2082
+  %54 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %51, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %17, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1 %18), !dbg !2082
   br i1 %54, label %60, label %55, !dbg !2083
 
 ; <label>:55:                                     ; preds = %50
@@ -10063,7 +10063,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriter
   %57 = bitcast %class.VaryingWriter* %19 to i8*, !dbg !2085
   %58 = bitcast %class.VaryingWriter* %1 to i8*, !dbg !2085
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 32 %57, i8* align 32 %58, i32 64, i1 false), !dbg !2085, !tbaa.struct !197
-  %59 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIPv13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %56, %class.VaryingWriter* byval align 32 %19, %"struct.PrintInfo::Encoding4Varying"* byval align 1 %20), !dbg !2086
+  %59 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIPv13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %56, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %19, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1 %20), !dbg !2086
   br label %60, !dbg !2083
 
 ; <label>:60:                                     ; preds = %55, %50, %45, %40, %35, %30, %25, %3
@@ -10072,7 +10072,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriter
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval align 32, %"struct.PrintInfo::Encoding4Varying"* byval align 1) #25 comdat !dbg !2088 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1) #25 comdat !dbg !2088 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -10098,7 +10098,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13Varyi
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval align 32, %"struct.PrintInfo::Encoding4Varying"* byval align 1) #25 comdat !dbg !2097 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1) #25 comdat !dbg !2097 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -10124,7 +10124,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13Varyi
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval align 32, %"struct.PrintInfo::Encoding4Varying"* byval align 1) #25 comdat !dbg !2106 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1) #25 comdat !dbg !2106 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -10150,7 +10150,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13Varyi
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval align 32, %"struct.PrintInfo::Encoding4Varying"* byval align 1) #25 comdat !dbg !2115 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1) #25 comdat !dbg !2115 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -10176,7 +10176,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13Varyi
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval align 32, %"struct.PrintInfo::Encoding4Varying"* byval align 1) #25 comdat !dbg !2124 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1) #25 comdat !dbg !2124 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -10202,7 +10202,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13Varyi
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval align 32, %"struct.PrintInfo::Encoding4Varying"* byval align 1) #25 comdat !dbg !2133 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1) #25 comdat !dbg !2133 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -10228,7 +10228,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13Varyi
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval align 32, %"struct.PrintInfo::Encoding4Varying"* byval align 1) #25 comdat !dbg !2142 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1) #25 comdat !dbg !2142 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -10254,7 +10254,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13Varyi
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIPv13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval align 32, %"struct.PrintInfo::Encoding4Varying"* byval align 1) #25 comdat !dbg !2151 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIPv13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1) #25 comdat !dbg !2151 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
diff --git a/builtins/builtins-cm-64.ll b/builtins/builtins-cm-64.ll
index 39a2dd8be..375d01bed 100644
--- a/builtins/builtins-cm-64.ll
+++ b/builtins/builtins-cm-64.ll
@@ -557,7 +557,7 @@ $_ZN13VaryingWriter12WriteVecElemIPvEEvv = comdat any
 @.str.10 = private unnamed_addr constant [8 x i8] c"%016llX\00", align 1
 
 ; Function Attrs: noinline nounwind
-define dso_local signext i8 @_Z24__cm_intrinsic_impl_sdivcc(i8 signext, i8 signext) #0 {
+define internal signext i8 @_Z24__cm_intrinsic_impl_sdivcc(i8 signext, i8 signext) #0 {
   %3 = alloca i8, align 1
   %4 = alloca i8, align 1
   %5 = alloca <1 x i8>, align 1
@@ -618,7 +618,7 @@ define internal <1 x i8> @_ZN7details13__impl_divremILi1EEEu2CMvbT__cS1_S1_u2CMv
 declare <1 x i8> @llvm.genx.rdregioni.v1i8.v1i8.i16(<1 x i8>, i32, i32, i32, i16, i32) #2
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i8> @_Z24__cm_intrinsic_impl_sdivu2CMvb1_cS_(<1 x i8>, <1 x i8>) #0 {
+define internal <1 x i8> @_Z24__cm_intrinsic_impl_sdivu2CMvb1_cS_(<1 x i8>, <1 x i8>) #0 {
   %3 = alloca <1 x i8>, align 1
   %4 = alloca <1 x i8>, align 1
   %5 = alloca <1 x i8>, align 1
@@ -634,7 +634,7 @@ define dso_local <1 x i8> @_Z24__cm_intrinsic_impl_sdivu2CMvb1_cS_(<1 x i8>, <1
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i8> @_Z24__cm_intrinsic_impl_sdivu2CMvb2_cS_(<2 x i8>, <2 x i8>) #3 {
+define internal <2 x i8> @_Z24__cm_intrinsic_impl_sdivu2CMvb2_cS_(<2 x i8>, <2 x i8>) #3 {
   %3 = alloca <2 x i8>, align 2
   %4 = alloca <2 x i8>, align 2
   %5 = alloca <2 x i8>, align 2
@@ -680,7 +680,7 @@ define internal <2 x i8> @_ZN7details13__impl_divremILi2EEEu2CMvbT__cS1_S1_u2CMv
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i8> @_Z24__cm_intrinsic_impl_sdivu2CMvb4_cS_(<4 x i8>, <4 x i8>) #5 {
+define internal <4 x i8> @_Z24__cm_intrinsic_impl_sdivu2CMvb4_cS_(<4 x i8>, <4 x i8>) #5 {
   %3 = alloca <4 x i8>, align 4
   %4 = alloca <4 x i8>, align 4
   %5 = alloca <4 x i8>, align 4
@@ -818,7 +818,7 @@ define internal <16 x i8> @_ZN7details13__impl_divremILi16EEEu2CMvbT__cS1_S1_u2C
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i8> @_Z24__cm_intrinsic_impl_sdivu2CMvb32_cS_(<32 x i8>, <32 x i8>) #11 {
+define internal <32 x i8> @_Z24__cm_intrinsic_impl_sdivu2CMvb32_cS_(<32 x i8>, <32 x i8>) #11 {
   %3 = alloca <32 x i8>, align 32
   %4 = alloca <32 x i8>, align 32
   %5 = alloca <32 x i8>, align 32
@@ -864,7 +864,7 @@ define internal <32 x i8> @_ZN7details13__impl_divremILi32EEEu2CMvbT__cS1_S1_u2C
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local signext i8 @_Z24__cm_intrinsic_impl_sremcc(i8 signext, i8 signext) #0 {
+define internal signext i8 @_Z24__cm_intrinsic_impl_sremcc(i8 signext, i8 signext) #0 {
   %3 = alloca i8, align 1
   %4 = alloca i8, align 1
   %5 = alloca <1 x i8>, align 1
@@ -890,7 +890,7 @@ define dso_local signext i8 @_Z24__cm_intrinsic_impl_sremcc(i8 signext, i8 signe
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb1_cS_(<1 x i8>, <1 x i8>) #0 {
+define internal <1 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb1_cS_(<1 x i8>, <1 x i8>) #0 {
   %3 = alloca <1 x i8>, align 1
   %4 = alloca <1 x i8>, align 1
   %5 = alloca <1 x i8>, align 1
@@ -904,7 +904,7 @@ define dso_local <1 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb1_cS_(<1 x i8>, <1
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb2_cS_(<2 x i8>, <2 x i8>) #3 {
+define internal <2 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb2_cS_(<2 x i8>, <2 x i8>) #3 {
   %3 = alloca <2 x i8>, align 2
   %4 = alloca <2 x i8>, align 2
   %5 = alloca <2 x i8>, align 2
@@ -918,7 +918,7 @@ define dso_local <2 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb2_cS_(<2 x i8>, <2
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb4_cS_(<4 x i8>, <4 x i8>) #5 {
+define internal <4 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb4_cS_(<4 x i8>, <4 x i8>) #5 {
   %3 = alloca <4 x i8>, align 4
   %4 = alloca <4 x i8>, align 4
   %5 = alloca <4 x i8>, align 4
@@ -932,7 +932,7 @@ define dso_local <4 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb4_cS_(<4 x i8>, <4
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <8 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb8_cS_(<8 x i8>, <8 x i8>) #7 {
+define internal <8 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb8_cS_(<8 x i8>, <8 x i8>) #7 {
   %3 = alloca <8 x i8>, align 8
   %4 = alloca <8 x i8>, align 8
   %5 = alloca <8 x i8>, align 8
@@ -946,7 +946,7 @@ define dso_local <8 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb8_cS_(<8 x i8>, <8
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <16 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb16_cS_(<16 x i8>, <16 x i8>) #9 {
+define internal <16 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb16_cS_(<16 x i8>, <16 x i8>) #9 {
   %3 = alloca <16 x i8>, align 16
   %4 = alloca <16 x i8>, align 16
   %5 = alloca <16 x i8>, align 16
@@ -960,7 +960,7 @@ define dso_local <16 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb16_cS_(<16 x i8>,
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb32_cS_(<32 x i8>, <32 x i8>) #11 {
+define internal <32 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb32_cS_(<32 x i8>, <32 x i8>) #11 {
   %3 = alloca <32 x i8>, align 32
   %4 = alloca <32 x i8>, align 32
   %5 = alloca <32 x i8>, align 32
@@ -974,7 +974,7 @@ define dso_local <32 x i8> @_Z24__cm_intrinsic_impl_sremu2CMvb32_cS_(<32 x i8>,
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local signext i16 @_Z24__cm_intrinsic_impl_sdivss(i16 signext, i16 signext) #3 {
+define internal signext i16 @_Z24__cm_intrinsic_impl_sdivss(i16 signext, i16 signext) #3 {
   %3 = alloca i16, align 2
   %4 = alloca i16, align 2
   %5 = alloca <1 x i16>, align 2
@@ -1058,7 +1058,7 @@ define internal <1 x i16> @_ZN7details13__impl_divremILi1EEEu2CMvbT__sS1_S1_u2CM
 declare <1 x i16> @llvm.genx.rdregioni.v1i16.v1i16.i16(<1 x i16>, i32, i32, i32, i16, i32) #2
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i16> @_Z24__cm_intrinsic_impl_sdivu2CMvb1_sS_(<1 x i16>, <1 x i16>) #3 {
+define internal <1 x i16> @_Z24__cm_intrinsic_impl_sdivu2CMvb1_sS_(<1 x i16>, <1 x i16>) #3 {
   %3 = alloca <1 x i16>, align 2
   %4 = alloca <1 x i16>, align 2
   %5 = alloca <1 x i16>, align 2
@@ -1074,7 +1074,7 @@ define dso_local <1 x i16> @_Z24__cm_intrinsic_impl_sdivu2CMvb1_sS_(<1 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i16> @_Z24__cm_intrinsic_impl_sdivu2CMvb2_sS_(<2 x i16>, <2 x i16>) #5 {
+define internal <2 x i16> @_Z24__cm_intrinsic_impl_sdivu2CMvb2_sS_(<2 x i16>, <2 x i16>) #5 {
   %3 = alloca <2 x i16>, align 4
   %4 = alloca <2 x i16>, align 4
   %5 = alloca <2 x i16>, align 4
@@ -1143,7 +1143,7 @@ define internal <2 x i16> @_ZN7details13__impl_divremILi2EEEu2CMvbT__sS1_S1_u2CM
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i16> @_Z24__cm_intrinsic_impl_sdivu2CMvb4_sS_(<4 x i16>, <4 x i16>) #7 {
+define internal <4 x i16> @_Z24__cm_intrinsic_impl_sdivu2CMvb4_sS_(<4 x i16>, <4 x i16>) #7 {
   %3 = alloca <4 x i16>, align 8
   %4 = alloca <4 x i16>, align 8
   %5 = alloca <4 x i16>, align 8
@@ -1350,7 +1350,7 @@ define internal <16 x i16> @_ZN7details13__impl_divremILi16EEEu2CMvbT__sS1_S1_u2
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i16> @_Z24__cm_intrinsic_impl_sdivu2CMvb32_sS_(<32 x i16>, <32 x i16>) #13 {
+define internal <32 x i16> @_Z24__cm_intrinsic_impl_sdivu2CMvb32_sS_(<32 x i16>, <32 x i16>) #13 {
   %3 = alloca <32 x i16>, align 64
   %4 = alloca <32 x i16>, align 64
   %5 = alloca <32 x i16>, align 64
@@ -1419,7 +1419,7 @@ define internal <32 x i16> @_ZN7details13__impl_divremILi32EEEu2CMvbT__sS1_S1_u2
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local signext i16 @_Z24__cm_intrinsic_impl_sremss(i16 signext, i16 signext) #3 {
+define internal signext i16 @_Z24__cm_intrinsic_impl_sremss(i16 signext, i16 signext) #3 {
   %3 = alloca i16, align 2
   %4 = alloca i16, align 2
   %5 = alloca <1 x i16>, align 2
@@ -1445,7 +1445,7 @@ define dso_local signext i16 @_Z24__cm_intrinsic_impl_sremss(i16 signext, i16 si
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb1_sS_(<1 x i16>, <1 x i16>) #3 {
+define internal <1 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb1_sS_(<1 x i16>, <1 x i16>) #3 {
   %3 = alloca <1 x i16>, align 2
   %4 = alloca <1 x i16>, align 2
   %5 = alloca <1 x i16>, align 2
@@ -1459,7 +1459,7 @@ define dso_local <1 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb1_sS_(<1 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb2_sS_(<2 x i16>, <2 x i16>) #5 {
+define internal <2 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb2_sS_(<2 x i16>, <2 x i16>) #5 {
   %3 = alloca <2 x i16>, align 4
   %4 = alloca <2 x i16>, align 4
   %5 = alloca <2 x i16>, align 4
@@ -1473,7 +1473,7 @@ define dso_local <2 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb2_sS_(<2 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb4_sS_(<4 x i16>, <4 x i16>) #7 {
+define internal <4 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb4_sS_(<4 x i16>, <4 x i16>) #7 {
   %3 = alloca <4 x i16>, align 8
   %4 = alloca <4 x i16>, align 8
   %5 = alloca <4 x i16>, align 8
@@ -1487,7 +1487,7 @@ define dso_local <4 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb4_sS_(<4 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <8 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb8_sS_(<8 x i16>, <8 x i16>) #9 {
+define internal <8 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb8_sS_(<8 x i16>, <8 x i16>) #9 {
   %3 = alloca <8 x i16>, align 16
   %4 = alloca <8 x i16>, align 16
   %5 = alloca <8 x i16>, align 16
@@ -1501,7 +1501,7 @@ define dso_local <8 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb8_sS_(<8 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <16 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb16_sS_(<16 x i16>, <16 x i16>) #11 {
+define internal <16 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb16_sS_(<16 x i16>, <16 x i16>) #11 {
   %3 = alloca <16 x i16>, align 32
   %4 = alloca <16 x i16>, align 32
   %5 = alloca <16 x i16>, align 32
@@ -1515,7 +1515,7 @@ define dso_local <16 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb16_sS_(<16 x i16>
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb32_sS_(<32 x i16>, <32 x i16>) #13 {
+define internal <32 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb32_sS_(<32 x i16>, <32 x i16>) #13 {
   %3 = alloca <32 x i16>, align 64
   %4 = alloca <32 x i16>, align 64
   %5 = alloca <32 x i16>, align 64
@@ -1529,7 +1529,7 @@ define dso_local <32 x i16> @_Z24__cm_intrinsic_impl_sremu2CMvb32_sS_(<32 x i16>
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local i32 @_Z24__cm_intrinsic_impl_sdivii(i32, i32) #14 {
+define internal i32 @_Z24__cm_intrinsic_impl_sdivii(i32, i32) #14 {
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
   %5 = alloca <1 x i32>, align 4
@@ -1730,7 +1730,7 @@ define internal <1 x i32> @_ZN7details13__impl_divremILi1EEEu2CMvbT__iS1_S1_u2CM
 declare <1 x i32> @llvm.genx.rdregioni.v1i32.v1i32.i16(<1 x i32>, i32, i32, i32, i16, i32) #2
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i32> @_Z24__cm_intrinsic_impl_sdivu2CMvb1_iS_(<1 x i32>, <1 x i32>) #14 {
+define internal <1 x i32> @_Z24__cm_intrinsic_impl_sdivu2CMvb1_iS_(<1 x i32>, <1 x i32>) #14 {
   %3 = alloca <1 x i32>, align 4
   %4 = alloca <1 x i32>, align 4
   %5 = alloca <1 x i32>, align 4
@@ -1746,7 +1746,7 @@ define dso_local <1 x i32> @_Z24__cm_intrinsic_impl_sdivu2CMvb1_iS_(<1 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i32> @_Z24__cm_intrinsic_impl_sdivu2CMvb2_iS_(<2 x i32>, <2 x i32>) #15 {
+define internal <2 x i32> @_Z24__cm_intrinsic_impl_sdivu2CMvb2_iS_(<2 x i32>, <2 x i32>) #15 {
   %3 = alloca <2 x i32>, align 8
   %4 = alloca <2 x i32>, align 8
   %5 = alloca <2 x i32>, align 8
@@ -1932,7 +1932,7 @@ define internal <2 x i32> @_ZN7details13__impl_divremILi2EEEu2CMvbT__iS1_S1_u2CM
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i32> @_Z24__cm_intrinsic_impl_sdivu2CMvb4_iS_(<4 x i32>, <4 x i32>) #16 {
+define internal <4 x i32> @_Z24__cm_intrinsic_impl_sdivu2CMvb4_iS_(<4 x i32>, <4 x i32>) #16 {
   %3 = alloca <4 x i32>, align 16
   %4 = alloca <4 x i32>, align 16
   %5 = alloca <4 x i32>, align 16
@@ -2490,7 +2490,7 @@ define internal <16 x i32> @_ZN7details13__impl_divremILi16EEEu2CMvbT__iS1_S1_u2
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i32> @_Z24__cm_intrinsic_impl_sdivu2CMvb32_iS_(<32 x i32>, <32 x i32>) #19 {
+define internal <32 x i32> @_Z24__cm_intrinsic_impl_sdivu2CMvb32_iS_(<32 x i32>, <32 x i32>) #19 {
   %3 = alloca <32 x i32>, align 128
   %4 = alloca <32 x i32>, align 128
   %5 = alloca <32 x i32>, align 128
@@ -2676,7 +2676,7 @@ define internal <32 x i32> @_ZN7details13__impl_divremILi32EEEu2CMvbT__iS1_S1_u2
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local i32 @_Z24__cm_intrinsic_impl_sremii(i32, i32) #14 {
+define internal i32 @_Z24__cm_intrinsic_impl_sremii(i32, i32) #14 {
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
   %5 = alloca <1 x i32>, align 4
@@ -2702,7 +2702,7 @@ define dso_local i32 @_Z24__cm_intrinsic_impl_sremii(i32, i32) #14 {
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb1_iS_(<1 x i32>, <1 x i32>) #14 {
+define internal <1 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb1_iS_(<1 x i32>, <1 x i32>) #14 {
   %3 = alloca <1 x i32>, align 4
   %4 = alloca <1 x i32>, align 4
   %5 = alloca <1 x i32>, align 4
@@ -2716,7 +2716,7 @@ define dso_local <1 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb1_iS_(<1 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb2_iS_(<2 x i32>, <2 x i32>) #15 {
+define internal <2 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb2_iS_(<2 x i32>, <2 x i32>) #15 {
   %3 = alloca <2 x i32>, align 8
   %4 = alloca <2 x i32>, align 8
   %5 = alloca <2 x i32>, align 8
@@ -2730,7 +2730,7 @@ define dso_local <2 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb2_iS_(<2 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb4_iS_(<4 x i32>, <4 x i32>) #16 {
+define internal <4 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb4_iS_(<4 x i32>, <4 x i32>) #16 {
   %3 = alloca <4 x i32>, align 16
   %4 = alloca <4 x i32>, align 16
   %5 = alloca <4 x i32>, align 16
@@ -2744,7 +2744,7 @@ define dso_local <4 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb4_iS_(<4 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <8 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb8_iS_(<8 x i32>, <8 x i32>) #17 {
+define internal <8 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb8_iS_(<8 x i32>, <8 x i32>) #17 {
   %3 = alloca <8 x i32>, align 32
   %4 = alloca <8 x i32>, align 32
   %5 = alloca <8 x i32>, align 32
@@ -2758,7 +2758,7 @@ define dso_local <8 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb8_iS_(<8 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <16 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb16_iS_(<16 x i32>, <16 x i32>) #18 {
+define internal <16 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb16_iS_(<16 x i32>, <16 x i32>) #18 {
   %3 = alloca <16 x i32>, align 64
   %4 = alloca <16 x i32>, align 64
   %5 = alloca <16 x i32>, align 64
@@ -2772,7 +2772,7 @@ define dso_local <16 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb16_iS_(<16 x i32>
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb32_iS_(<32 x i32>, <32 x i32>) #19 {
+define internal <32 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb32_iS_(<32 x i32>, <32 x i32>) #19 {
   %3 = alloca <32 x i32>, align 128
   %4 = alloca <32 x i32>, align 128
   %5 = alloca <32 x i32>, align 128
@@ -2786,7 +2786,7 @@ define dso_local <32 x i32> @_Z24__cm_intrinsic_impl_sremu2CMvb32_iS_(<32 x i32>
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local zeroext i8 @_Z24__cm_intrinsic_impl_udivhh(i8 zeroext, i8 zeroext) #21 {
+define internal zeroext i8 @_Z24__cm_intrinsic_impl_udivhh(i8 zeroext, i8 zeroext) #21 {
   %3 = alloca i8, align 1
   %4 = alloca i8, align 1
   %5 = alloca <1 x i8>, align 1
@@ -2844,7 +2844,7 @@ define internal <1 x i8> @_ZN7details14__impl_udivremILi1EEEu2CMvbT__hS1_S1_u2CM
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i8> @_Z24__cm_intrinsic_impl_udivu2CMvb1_hS_(<1 x i8>, <1 x i8>) #21 {
+define internal <1 x i8> @_Z24__cm_intrinsic_impl_udivu2CMvb1_hS_(<1 x i8>, <1 x i8>) #21 {
   %3 = alloca <1 x i8>, align 1
   %4 = alloca <1 x i8>, align 1
   %5 = alloca <1 x i8>, align 1
@@ -2860,7 +2860,7 @@ define dso_local <1 x i8> @_Z24__cm_intrinsic_impl_udivu2CMvb1_hS_(<1 x i8>, <1
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i8> @_Z24__cm_intrinsic_impl_udivu2CMvb2_hS_(<2 x i8>, <2 x i8>) #22 {
+define internal <2 x i8> @_Z24__cm_intrinsic_impl_udivu2CMvb2_hS_(<2 x i8>, <2 x i8>) #22 {
   %3 = alloca <2 x i8>, align 2
   %4 = alloca <2 x i8>, align 2
   %5 = alloca <2 x i8>, align 2
@@ -2906,7 +2906,7 @@ define internal <2 x i8> @_ZN7details14__impl_udivremILi2EEEu2CMvbT__hS1_S1_u2CM
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i8> @_Z24__cm_intrinsic_impl_udivu2CMvb4_hS_(<4 x i8>, <4 x i8>) #14 {
+define internal <4 x i8> @_Z24__cm_intrinsic_impl_udivu2CMvb4_hS_(<4 x i8>, <4 x i8>) #14 {
   %3 = alloca <4 x i8>, align 4
   %4 = alloca <4 x i8>, align 4
   %5 = alloca <4 x i8>, align 4
@@ -3044,7 +3044,7 @@ define internal <16 x i8> @_ZN7details14__impl_udivremILi16EEEu2CMvbT__hS1_S1_u2
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i8> @_Z24__cm_intrinsic_impl_udivu2CMvb32_hS_(<32 x i8>, <32 x i8>) #17 {
+define internal <32 x i8> @_Z24__cm_intrinsic_impl_udivu2CMvb32_hS_(<32 x i8>, <32 x i8>) #17 {
   %3 = alloca <32 x i8>, align 32
   %4 = alloca <32 x i8>, align 32
   %5 = alloca <32 x i8>, align 32
@@ -3090,7 +3090,7 @@ define internal <32 x i8> @_ZN7details14__impl_udivremILi32EEEu2CMvbT__hS1_S1_u2
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local zeroext i8 @_Z24__cm_intrinsic_impl_uremhh(i8 zeroext, i8 zeroext) #21 {
+define internal zeroext i8 @_Z24__cm_intrinsic_impl_uremhh(i8 zeroext, i8 zeroext) #21 {
   %3 = alloca i8, align 1
   %4 = alloca i8, align 1
   %5 = alloca <1 x i8>, align 1
@@ -3116,7 +3116,7 @@ define dso_local zeroext i8 @_Z24__cm_intrinsic_impl_uremhh(i8 zeroext, i8 zeroe
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb1_hS_(<1 x i8>, <1 x i8>) #21 {
+define internal <1 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb1_hS_(<1 x i8>, <1 x i8>) #21 {
   %3 = alloca <1 x i8>, align 1
   %4 = alloca <1 x i8>, align 1
   %5 = alloca <1 x i8>, align 1
@@ -3130,7 +3130,7 @@ define dso_local <1 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb1_hS_(<1 x i8>, <1
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb2_hS_(<2 x i8>, <2 x i8>) #22 {
+define internal <2 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb2_hS_(<2 x i8>, <2 x i8>) #22 {
   %3 = alloca <2 x i8>, align 2
   %4 = alloca <2 x i8>, align 2
   %5 = alloca <2 x i8>, align 2
@@ -3144,7 +3144,7 @@ define dso_local <2 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb2_hS_(<2 x i8>, <2
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb4_hS_(<4 x i8>, <4 x i8>) #14 {
+define internal <4 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb4_hS_(<4 x i8>, <4 x i8>) #14 {
   %3 = alloca <4 x i8>, align 4
   %4 = alloca <4 x i8>, align 4
   %5 = alloca <4 x i8>, align 4
@@ -3158,7 +3158,7 @@ define dso_local <4 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb4_hS_(<4 x i8>, <4
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <8 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb8_hS_(<8 x i8>, <8 x i8>) #15 {
+define internal <8 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb8_hS_(<8 x i8>, <8 x i8>) #15 {
   %3 = alloca <8 x i8>, align 8
   %4 = alloca <8 x i8>, align 8
   %5 = alloca <8 x i8>, align 8
@@ -3172,7 +3172,7 @@ define dso_local <8 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb8_hS_(<8 x i8>, <8
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <16 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb16_hS_(<16 x i8>, <16 x i8>) #16 {
+define internal <16 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb16_hS_(<16 x i8>, <16 x i8>) #16 {
   %3 = alloca <16 x i8>, align 16
   %4 = alloca <16 x i8>, align 16
   %5 = alloca <16 x i8>, align 16
@@ -3186,7 +3186,7 @@ define dso_local <16 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb16_hS_(<16 x i8>,
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb32_hS_(<32 x i8>, <32 x i8>) #17 {
+define internal <32 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb32_hS_(<32 x i8>, <32 x i8>) #17 {
   %3 = alloca <32 x i8>, align 32
   %4 = alloca <32 x i8>, align 32
   %5 = alloca <32 x i8>, align 32
@@ -3200,7 +3200,7 @@ define dso_local <32 x i8> @_Z24__cm_intrinsic_impl_uremu2CMvb32_hS_(<32 x i8>,
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local zeroext i16 @_Z24__cm_intrinsic_impl_udivtt(i16 zeroext, i16 zeroext) #22 {
+define internal zeroext i16 @_Z24__cm_intrinsic_impl_udivtt(i16 zeroext, i16 zeroext) #22 {
   %3 = alloca i16, align 2
   %4 = alloca i16, align 2
   %5 = alloca <1 x i16>, align 2
@@ -3278,7 +3278,7 @@ define internal <1 x i16> @_ZN7details14__impl_udivremILi1EEEu2CMvbT__tS1_S1_u2C
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i16> @_Z24__cm_intrinsic_impl_udivu2CMvb1_tS_(<1 x i16>, <1 x i16>) #22 {
+define internal <1 x i16> @_Z24__cm_intrinsic_impl_udivu2CMvb1_tS_(<1 x i16>, <1 x i16>) #22 {
   %3 = alloca <1 x i16>, align 2
   %4 = alloca <1 x i16>, align 2
   %5 = alloca <1 x i16>, align 2
@@ -3294,7 +3294,7 @@ define dso_local <1 x i16> @_Z24__cm_intrinsic_impl_udivu2CMvb1_tS_(<1 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i16> @_Z24__cm_intrinsic_impl_udivu2CMvb2_tS_(<2 x i16>, <2 x i16>) #14 {
+define internal <2 x i16> @_Z24__cm_intrinsic_impl_udivu2CMvb2_tS_(<2 x i16>, <2 x i16>) #14 {
   %3 = alloca <2 x i16>, align 4
   %4 = alloca <2 x i16>, align 4
   %5 = alloca <2 x i16>, align 4
@@ -3360,7 +3360,7 @@ define internal <2 x i16> @_ZN7details14__impl_udivremILi2EEEu2CMvbT__tS1_S1_u2C
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i16> @_Z24__cm_intrinsic_impl_udivu2CMvb4_tS_(<4 x i16>, <4 x i16>) #15 {
+define internal <4 x i16> @_Z24__cm_intrinsic_impl_udivu2CMvb4_tS_(<4 x i16>, <4 x i16>) #15 {
   %3 = alloca <4 x i16>, align 8
   %4 = alloca <4 x i16>, align 8
   %5 = alloca <4 x i16>, align 8
@@ -3558,7 +3558,7 @@ define internal <16 x i16> @_ZN7details14__impl_udivremILi16EEEu2CMvbT__tS1_S1_u
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i16> @_Z24__cm_intrinsic_impl_udivu2CMvb32_tS_(<32 x i16>, <32 x i16>) #18 {
+define internal <32 x i16> @_Z24__cm_intrinsic_impl_udivu2CMvb32_tS_(<32 x i16>, <32 x i16>) #18 {
   %3 = alloca <32 x i16>, align 64
   %4 = alloca <32 x i16>, align 64
   %5 = alloca <32 x i16>, align 64
@@ -3624,7 +3624,7 @@ define internal <32 x i16> @_ZN7details14__impl_udivremILi32EEEu2CMvbT__tS1_S1_u
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local zeroext i16 @_Z24__cm_intrinsic_impl_uremtt(i16 zeroext, i16 zeroext) #22 {
+define internal zeroext i16 @_Z24__cm_intrinsic_impl_uremtt(i16 zeroext, i16 zeroext) #22 {
   %3 = alloca i16, align 2
   %4 = alloca i16, align 2
   %5 = alloca <1 x i16>, align 2
@@ -3650,7 +3650,7 @@ define dso_local zeroext i16 @_Z24__cm_intrinsic_impl_uremtt(i16 zeroext, i16 ze
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb1_tS_(<1 x i16>, <1 x i16>) #22 {
+define internal <1 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb1_tS_(<1 x i16>, <1 x i16>) #22 {
   %3 = alloca <1 x i16>, align 2
   %4 = alloca <1 x i16>, align 2
   %5 = alloca <1 x i16>, align 2
@@ -3664,7 +3664,7 @@ define dso_local <1 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb1_tS_(<1 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb2_tS_(<2 x i16>, <2 x i16>) #14 {
+define internal <2 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb2_tS_(<2 x i16>, <2 x i16>) #14 {
   %3 = alloca <2 x i16>, align 4
   %4 = alloca <2 x i16>, align 4
   %5 = alloca <2 x i16>, align 4
@@ -3678,7 +3678,7 @@ define dso_local <2 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb2_tS_(<2 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb4_tS_(<4 x i16>, <4 x i16>) #15 {
+define internal <4 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb4_tS_(<4 x i16>, <4 x i16>) #15 {
   %3 = alloca <4 x i16>, align 8
   %4 = alloca <4 x i16>, align 8
   %5 = alloca <4 x i16>, align 8
@@ -3692,7 +3692,7 @@ define dso_local <4 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb4_tS_(<4 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <8 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb8_tS_(<8 x i16>, <8 x i16>) #16 {
+define internal <8 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb8_tS_(<8 x i16>, <8 x i16>) #16 {
   %3 = alloca <8 x i16>, align 16
   %4 = alloca <8 x i16>, align 16
   %5 = alloca <8 x i16>, align 16
@@ -3706,7 +3706,7 @@ define dso_local <8 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb8_tS_(<8 x i16>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <16 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb16_tS_(<16 x i16>, <16 x i16>) #17 {
+define internal <16 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb16_tS_(<16 x i16>, <16 x i16>) #17 {
   %3 = alloca <16 x i16>, align 32
   %4 = alloca <16 x i16>, align 32
   %5 = alloca <16 x i16>, align 32
@@ -3720,7 +3720,7 @@ define dso_local <16 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb16_tS_(<16 x i16>
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb32_tS_(<32 x i16>, <32 x i16>) #18 {
+define internal <32 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb32_tS_(<32 x i16>, <32 x i16>) #18 {
   %3 = alloca <32 x i16>, align 64
   %4 = alloca <32 x i16>, align 64
   %5 = alloca <32 x i16>, align 64
@@ -3734,7 +3734,7 @@ define dso_local <32 x i16> @_Z24__cm_intrinsic_impl_uremu2CMvb32_tS_(<32 x i16>
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local i32 @_Z24__cm_intrinsic_impl_udivjj(i32, i32) #14 {
+define internal i32 @_Z24__cm_intrinsic_impl_udivjj(i32, i32) #14 {
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
   %5 = alloca <1 x i32>, align 4
@@ -3892,7 +3892,7 @@ define internal <1 x i32> @_ZN7details14__impl_udivremILi1EEEu2CMvbT__jS1_S1_u2C
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i32> @_Z24__cm_intrinsic_impl_udivu2CMvb1_jS_(<1 x i32>, <1 x i32>) #14 {
+define internal <1 x i32> @_Z24__cm_intrinsic_impl_udivu2CMvb1_jS_(<1 x i32>, <1 x i32>) #14 {
   %3 = alloca <1 x i32>, align 4
   %4 = alloca <1 x i32>, align 4
   %5 = alloca <1 x i32>, align 4
@@ -3908,7 +3908,7 @@ define dso_local <1 x i32> @_Z24__cm_intrinsic_impl_udivu2CMvb1_jS_(<1 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i32> @_Z24__cm_intrinsic_impl_udivu2CMvb2_jS_(<2 x i32>, <2 x i32>) #15 {
+define internal <2 x i32> @_Z24__cm_intrinsic_impl_udivu2CMvb2_jS_(<2 x i32>, <2 x i32>) #15 {
   %3 = alloca <2 x i32>, align 8
   %4 = alloca <2 x i32>, align 8
   %5 = alloca <2 x i32>, align 8
@@ -4054,7 +4054,7 @@ define internal <2 x i32> @_ZN7details14__impl_udivremILi2EEEu2CMvbT__jS1_S1_u2C
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i32> @_Z24__cm_intrinsic_impl_udivu2CMvb4_jS_(<4 x i32>, <4 x i32>) #16 {
+define internal <4 x i32> @_Z24__cm_intrinsic_impl_udivu2CMvb4_jS_(<4 x i32>, <4 x i32>) #16 {
   %3 = alloca <4 x i32>, align 16
   %4 = alloca <4 x i32>, align 16
   %5 = alloca <4 x i32>, align 16
@@ -4492,7 +4492,7 @@ define internal <16 x i32> @_ZN7details14__impl_udivremILi16EEEu2CMvbT__jS1_S1_u
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i32> @_Z24__cm_intrinsic_impl_udivu2CMvb32_jS_(<32 x i32>, <32 x i32>) #19 {
+define internal <32 x i32> @_Z24__cm_intrinsic_impl_udivu2CMvb32_jS_(<32 x i32>, <32 x i32>) #19 {
   %3 = alloca <32 x i32>, align 128
   %4 = alloca <32 x i32>, align 128
   %5 = alloca <32 x i32>, align 128
@@ -4638,7 +4638,7 @@ define internal <32 x i32> @_ZN7details14__impl_udivremILi32EEEu2CMvbT__jS1_S1_u
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local i32 @_Z24__cm_intrinsic_impl_uremjj(i32, i32) #14 {
+define internal i32 @_Z24__cm_intrinsic_impl_uremjj(i32, i32) #14 {
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
   %5 = alloca <1 x i32>, align 4
@@ -4664,7 +4664,7 @@ define dso_local i32 @_Z24__cm_intrinsic_impl_uremjj(i32, i32) #14 {
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <1 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb1_jS_(<1 x i32>, <1 x i32>) #14 {
+define internal <1 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb1_jS_(<1 x i32>, <1 x i32>) #14 {
   %3 = alloca <1 x i32>, align 4
   %4 = alloca <1 x i32>, align 4
   %5 = alloca <1 x i32>, align 4
@@ -4678,7 +4678,7 @@ define dso_local <1 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb1_jS_(<1 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <2 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb2_jS_(<2 x i32>, <2 x i32>) #15 {
+define internal <2 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb2_jS_(<2 x i32>, <2 x i32>) #15 {
   %3 = alloca <2 x i32>, align 8
   %4 = alloca <2 x i32>, align 8
   %5 = alloca <2 x i32>, align 8
@@ -4692,7 +4692,7 @@ define dso_local <2 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb2_jS_(<2 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <4 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb4_jS_(<4 x i32>, <4 x i32>) #16 {
+define internal <4 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb4_jS_(<4 x i32>, <4 x i32>) #16 {
   %3 = alloca <4 x i32>, align 16
   %4 = alloca <4 x i32>, align 16
   %5 = alloca <4 x i32>, align 16
@@ -4706,7 +4706,7 @@ define dso_local <4 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb4_jS_(<4 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <8 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb8_jS_(<8 x i32>, <8 x i32>) #17 {
+define internal <8 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb8_jS_(<8 x i32>, <8 x i32>) #17 {
   %3 = alloca <8 x i32>, align 32
   %4 = alloca <8 x i32>, align 32
   %5 = alloca <8 x i32>, align 32
@@ -4720,7 +4720,7 @@ define dso_local <8 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb8_jS_(<8 x i32>, <
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <16 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb16_jS_(<16 x i32>, <16 x i32>) #18 {
+define internal <16 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb16_jS_(<16 x i32>, <16 x i32>) #18 {
   %3 = alloca <16 x i32>, align 64
   %4 = alloca <16 x i32>, align 64
   %5 = alloca <16 x i32>, align 64
@@ -4734,7 +4734,7 @@ define dso_local <16 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb16_jS_(<16 x i32>
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local <32 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb32_jS_(<32 x i32>, <32 x i32>) #19 {
+define internal <32 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb32_jS_(<32 x i32>, <32 x i32>) #19 {
   %3 = alloca <32 x i32>, align 128
   %4 = alloca <32 x i32>, align 128
   %5 = alloca <32 x i32>, align 128
@@ -4748,7 +4748,7 @@ define dso_local <32 x i32> @_Z24__cm_intrinsic_impl_uremu2CMvb32_jS_(<32 x i32>
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local void @__do_print_cm(i8*, i8*, i32, i64, i32*, i32, i32) #23 !dbg !15 {
+define internal void @__do_print_cm(i8*, i8*, i32, i64, i32*, i32, i32) #23 !dbg !15 {
   %8 = alloca i8*, align 8
   %9 = alloca i8*, align 8
   %10 = alloca i32, align 4
@@ -5070,7 +5070,7 @@ define dso_local void @__do_print_lz(i32, i8*, i32, i64, i32*, i32, i32, i32, i3
   %67 = load i64, i64* %13, align 8, !dbg !159, !tbaa !19
   %68 = load <5 x i32>, <5 x i32>* %21, align 32, !dbg !160, !tbaa !7
   call void @_ZN13VaryingWriterC2ERyRPKjiyu2CMvb5_i(%class.VaryingWriter* %23, i64* dereferenceable(8) %19, i32** dereferenceable(8) %14, i32 %66, i64 %67, <5 x i32> %68), !dbg !161
-  %69 = call zeroext i1 @_ZN9PrintInfo14switchEncodingI13UniformWriter13VaryingWriterEEbNS_8EncodingET_T0_(i8 signext %62, %class.UniformWriter* byval align 32 %22, %class.VaryingWriter* byval align 32 %23), !dbg !162
+  %69 = call zeroext i1 @_ZN9PrintInfo14switchEncodingI13UniformWriter13VaryingWriterEEbNS_8EncodingET_T0_(i8 signext %62, %class.UniformWriter* byval(%class.UniformWriter) align 32 %22, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %23), !dbg !162
   br label %70, !dbg !163
 
 ; <label>:70:                                     ; preds = %60
@@ -5188,7 +5188,7 @@ define internal <5 x i32> @_Z17get_auxiliary_strv() #28 comdat !dbg !178 {
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo14switchEncodingI13UniformWriter13VaryingWriterEEbNS_8EncodingET_T0_(i8 signext, %class.UniformWriter* byval align 32, %class.VaryingWriter* byval align 32) #25 comdat !dbg !191 {
+define internal zeroext i1 @_ZN9PrintInfo14switchEncodingI13UniformWriter13VaryingWriterEEbNS_8EncodingET_T0_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %class.VaryingWriter* byval(%class.VaryingWriter) align 32) #25 comdat !dbg !191 {
   %4 = alloca i8, align 1
   %5 = alloca %class.UniformWriter, align 32
   %6 = alloca %class.VaryingWriter, align 32
@@ -5197,7 +5197,7 @@ define internal zeroext i1 @_ZN9PrintInfo14switchEncodingI13UniformWriter13Varyi
   %8 = bitcast %class.UniformWriter* %5 to i8*, !dbg !196
   %9 = bitcast %class.UniformWriter* %1 to i8*, !dbg !196
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %8, i8* align 32 %9, i64 64, i1 false), !dbg !196, !tbaa.struct !197
-  %10 = call zeroext i1 @_ZN9PrintInfo22switchEncoding4UniformI13UniformWriterEEbNS_8EncodingET_(i8 signext %7, %class.UniformWriter* byval align 32 %5), !dbg !198
+  %10 = call zeroext i1 @_ZN9PrintInfo22switchEncoding4UniformI13UniformWriterEEbNS_8EncodingET_(i8 signext %7, %class.UniformWriter* byval(%class.UniformWriter) align 32 %5), !dbg !198
   br i1 %10, label %16, label %11, !dbg !199
 
 ; <label>:11:                                     ; preds = %3
@@ -5205,7 +5205,7 @@ define internal zeroext i1 @_ZN9PrintInfo14switchEncodingI13UniformWriter13Varyi
   %13 = bitcast %class.VaryingWriter* %6 to i8*, !dbg !201
   %14 = bitcast %class.VaryingWriter* %2 to i8*, !dbg !201
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %13, i8* align 32 %14, i64 64, i1 false), !dbg !201, !tbaa.struct !197
-  %15 = call zeroext i1 @_ZN9PrintInfo22switchEncoding4VaryingI13VaryingWriterEEbNS_8EncodingET_(i8 signext %12, %class.VaryingWriter* byval align 32 %6), !dbg !202
+  %15 = call zeroext i1 @_ZN9PrintInfo22switchEncoding4VaryingI13VaryingWriterEEbNS_8EncodingET_(i8 signext %12, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %6), !dbg !202
   br label %16, !dbg !199
 
 ; <label>:16:                                     ; preds = %11, %3
@@ -5280,7 +5280,7 @@ define internal void @_ZN13VaryingWriterC2ERyRPKjiyu2CMvb5_i(%class.VaryingWrite
 }
 
 ; Function Attrs: noinline nounwind
-define dso_local i32 @__num_cores() #29 !dbg !236 {
+define internal i32 @__num_cores() #29 !dbg !236 {
   ret i32 -1, !dbg !237
 }
 
@@ -8870,7 +8870,7 @@ declare dso_local void @_ZN7details37__cm_intrinsic_impl_svm_scatter_writeIiLi1E
 declare void @llvm.genx.svm.scatter.v1i1.v1i64.v1i32(<1 x i1>, i32, <1 x i64>, <1 x i32>) #27
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo22switchEncoding4UniformI13UniformWriterEEbNS_8EncodingET_(i8 signext, %class.UniformWriter* byval align 32) #25 comdat !dbg !1645 {
+define internal zeroext i1 @_ZN9PrintInfo22switchEncoding4UniformI13UniformWriterEEbNS_8EncodingET_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32) #25 comdat !dbg !1645 {
   %3 = alloca i8, align 1
   %4 = alloca %class.UniformWriter, align 32
   %5 = alloca %"struct.PrintInfo::Encoding4Uniform", align 1
@@ -8879,7 +8879,7 @@ define internal zeroext i1 @_ZN9PrintInfo22switchEncoding4UniformI13UniformWrite
   %7 = bitcast %class.UniformWriter* %4 to i8*, !dbg !1647
   %8 = bitcast %class.UniformWriter* %1 to i8*, !dbg !1647
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %7, i8* align 32 %8, i64 64, i1 false), !dbg !1647, !tbaa.struct !197
-  %9 = call zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET_T0_(i8 signext %6, %class.UniformWriter* byval align 32 %4, %"struct.PrintInfo::Encoding4Uniform"* byval align 1 %5), !dbg !1648
+  %9 = call zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET_T0_(i8 signext %6, %class.UniformWriter* byval(%class.UniformWriter) align 32 %4, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1 %5), !dbg !1648
   ret i1 %9, !dbg !1649
 }
 
@@ -8887,7 +8887,7 @@ define internal zeroext i1 @_ZN9PrintInfo22switchEncoding4UniformI13UniformWrite
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1) #32
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo22switchEncoding4VaryingI13VaryingWriterEEbNS_8EncodingET_(i8 signext, %class.VaryingWriter* byval align 32) #25 comdat !dbg !1650 {
+define internal zeroext i1 @_ZN9PrintInfo22switchEncoding4VaryingI13VaryingWriterEEbNS_8EncodingET_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32) #25 comdat !dbg !1650 {
   %3 = alloca i8, align 1
   %4 = alloca %class.VaryingWriter, align 32
   %5 = alloca %"struct.PrintInfo::Encoding4Varying", align 1
@@ -8896,12 +8896,12 @@ define internal zeroext i1 @_ZN9PrintInfo22switchEncoding4VaryingI13VaryingWrite
   %7 = bitcast %class.VaryingWriter* %4 to i8*, !dbg !1652
   %8 = bitcast %class.VaryingWriter* %1 to i8*, !dbg !1652
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %7, i8* align 32 %8, i64 64, i1 false), !dbg !1652, !tbaa.struct !197
-  %9 = call zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET_T0_(i8 signext %6, %class.VaryingWriter* byval align 32 %4, %"struct.PrintInfo::Encoding4Varying"* byval align 1 %5), !dbg !1653
+  %9 = call zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET_T0_(i8 signext %6, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %4, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1 %5), !dbg !1653
   ret i1 %9, !dbg !1654
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET_T0_(i8 signext, %class.UniformWriter* byval align 32, %"struct.PrintInfo::Encoding4Uniform"* byval align 1) #25 comdat !dbg !1655 {
+define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET_T0_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1) #25 comdat !dbg !1655 {
   %4 = alloca i8, align 1
   %5 = alloca %class.UniformWriter, align 32
   %6 = alloca %"struct.PrintInfo::Encoding4Uniform", align 1
@@ -8924,7 +8924,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriter
   %22 = bitcast %class.UniformWriter* %5 to i8*, !dbg !1657
   %23 = bitcast %class.UniformWriter* %1 to i8*, !dbg !1657
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %22, i8* align 32 %23, i64 64, i1 false), !dbg !1657, !tbaa.struct !197
-  %24 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %21, %class.UniformWriter* byval align 32 %5, %"struct.PrintInfo::Encoding4Uniform"* byval align 1 %6), !dbg !1658
+  %24 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %21, %class.UniformWriter* byval(%class.UniformWriter) align 32 %5, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1 %6), !dbg !1658
   br i1 %24, label %60, label %25, !dbg !1659
 
 ; <label>:25:                                     ; preds = %3
@@ -8932,7 +8932,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriter
   %27 = bitcast %class.UniformWriter* %7 to i8*, !dbg !1661
   %28 = bitcast %class.UniformWriter* %1 to i8*, !dbg !1661
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %27, i8* align 32 %28, i64 64, i1 false), !dbg !1661, !tbaa.struct !197
-  %29 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %26, %class.UniformWriter* byval align 32 %7, %"struct.PrintInfo::Encoding4Uniform"* byval align 1 %8), !dbg !1662
+  %29 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %26, %class.UniformWriter* byval(%class.UniformWriter) align 32 %7, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1 %8), !dbg !1662
   br i1 %29, label %60, label %30, !dbg !1663
 
 ; <label>:30:                                     ; preds = %25
@@ -8940,7 +8940,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriter
   %32 = bitcast %class.UniformWriter* %9 to i8*, !dbg !1665
   %33 = bitcast %class.UniformWriter* %1 to i8*, !dbg !1665
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %32, i8* align 32 %33, i64 64, i1 false), !dbg !1665, !tbaa.struct !197
-  %34 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %31, %class.UniformWriter* byval align 32 %9, %"struct.PrintInfo::Encoding4Uniform"* byval align 1 %10), !dbg !1666
+  %34 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %31, %class.UniformWriter* byval(%class.UniformWriter) align 32 %9, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1 %10), !dbg !1666
   br i1 %34, label %60, label %35, !dbg !1667
 
 ; <label>:35:                                     ; preds = %30
@@ -8948,7 +8948,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriter
   %37 = bitcast %class.UniformWriter* %11 to i8*, !dbg !1669
   %38 = bitcast %class.UniformWriter* %1 to i8*, !dbg !1669
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %37, i8* align 32 %38, i64 64, i1 false), !dbg !1669, !tbaa.struct !197
-  %39 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %36, %class.UniformWriter* byval align 32 %11, %"struct.PrintInfo::Encoding4Uniform"* byval align 1 %12), !dbg !1670
+  %39 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %36, %class.UniformWriter* byval(%class.UniformWriter) align 32 %11, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1 %12), !dbg !1670
   br i1 %39, label %60, label %40, !dbg !1671
 
 ; <label>:40:                                     ; preds = %35
@@ -8956,7 +8956,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriter
   %42 = bitcast %class.UniformWriter* %13 to i8*, !dbg !1673
   %43 = bitcast %class.UniformWriter* %1 to i8*, !dbg !1673
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %42, i8* align 32 %43, i64 64, i1 false), !dbg !1673, !tbaa.struct !197
-  %44 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %41, %class.UniformWriter* byval align 32 %13, %"struct.PrintInfo::Encoding4Uniform"* byval align 1 %14), !dbg !1674
+  %44 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %41, %class.UniformWriter* byval(%class.UniformWriter) align 32 %13, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1 %14), !dbg !1674
   br i1 %44, label %60, label %45, !dbg !1675
 
 ; <label>:45:                                     ; preds = %40
@@ -8964,7 +8964,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriter
   %47 = bitcast %class.UniformWriter* %15 to i8*, !dbg !1677
   %48 = bitcast %class.UniformWriter* %1 to i8*, !dbg !1677
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %47, i8* align 32 %48, i64 64, i1 false), !dbg !1677, !tbaa.struct !197
-  %49 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %46, %class.UniformWriter* byval align 32 %15, %"struct.PrintInfo::Encoding4Uniform"* byval align 1 %16), !dbg !1678
+  %49 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %46, %class.UniformWriter* byval(%class.UniformWriter) align 32 %15, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1 %16), !dbg !1678
   br i1 %49, label %60, label %50, !dbg !1679
 
 ; <label>:50:                                     ; preds = %45
@@ -8972,7 +8972,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriter
   %52 = bitcast %class.UniformWriter* %17 to i8*, !dbg !1681
   %53 = bitcast %class.UniformWriter* %1 to i8*, !dbg !1681
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %52, i8* align 32 %53, i64 64, i1 false), !dbg !1681, !tbaa.struct !197
-  %54 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %51, %class.UniformWriter* byval align 32 %17, %"struct.PrintInfo::Encoding4Uniform"* byval align 1 %18), !dbg !1682
+  %54 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %51, %class.UniformWriter* byval(%class.UniformWriter) align 32 %17, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1 %18), !dbg !1682
   br i1 %54, label %60, label %55, !dbg !1683
 
 ; <label>:55:                                     ; preds = %50
@@ -8980,7 +8980,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriter
   %57 = bitcast %class.UniformWriter* %19 to i8*, !dbg !1685
   %58 = bitcast %class.UniformWriter* %1 to i8*, !dbg !1685
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %57, i8* align 32 %58, i64 64, i1 false), !dbg !1685, !tbaa.struct !197
-  %59 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIPv13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %56, %class.UniformWriter* byval align 32 %19, %"struct.PrintInfo::Encoding4Uniform"* byval align 1 %20), !dbg !1686
+  %59 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIPv13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext %56, %class.UniformWriter* byval(%class.UniformWriter) align 32 %19, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1 %20), !dbg !1686
   br label %60, !dbg !1683
 
 ; <label>:60:                                     ; preds = %55, %50, %45, %40, %35, %30, %25, %3
@@ -8989,7 +8989,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13UniformWriter
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval align 32, %"struct.PrintInfo::Encoding4Uniform"* byval align 1) #25 comdat !dbg !1688 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1) #25 comdat !dbg !1688 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -9015,7 +9015,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13Unifo
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval align 32, %"struct.PrintInfo::Encoding4Uniform"* byval align 1) #25 comdat !dbg !1697 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1) #25 comdat !dbg !1697 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -9041,7 +9041,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13Unifo
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval align 32, %"struct.PrintInfo::Encoding4Uniform"* byval align 1) #25 comdat !dbg !1706 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1) #25 comdat !dbg !1706 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -9067,7 +9067,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13Unifo
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval align 32, %"struct.PrintInfo::Encoding4Uniform"* byval align 1) #25 comdat !dbg !1715 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1) #25 comdat !dbg !1715 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -9093,7 +9093,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13Unifo
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval align 32, %"struct.PrintInfo::Encoding4Uniform"* byval align 1) #25 comdat !dbg !1724 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1) #25 comdat !dbg !1724 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -9119,7 +9119,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13Unifo
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval align 32, %"struct.PrintInfo::Encoding4Uniform"* byval align 1) #25 comdat !dbg !1733 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1) #25 comdat !dbg !1733 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -9145,7 +9145,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13Unifo
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval align 32, %"struct.PrintInfo::Encoding4Uniform"* byval align 1) #25 comdat !dbg !1742 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1) #25 comdat !dbg !1742 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -9171,7 +9171,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13Unifo
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIPv13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval align 32, %"struct.PrintInfo::Encoding4Uniform"* byval align 1) #25 comdat !dbg !1751 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIPv13UniformWriterNS_16Encoding4UniformEEEbNS_8EncodingET0_T1_(i8 signext, %class.UniformWriter* byval(%class.UniformWriter) align 32, %"struct.PrintInfo::Encoding4Uniform"* byval(%"struct.PrintInfo::Encoding4Uniform") align 1) #25 comdat !dbg !1751 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -10013,7 +10013,7 @@ define internal i32 @_ZN7details18_cm_print_type_oclIPvEENS_18SHADER_PRINTF_TYPE
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET_T0_(i8 signext, %class.VaryingWriter* byval align 32, %"struct.PrintInfo::Encoding4Varying"* byval align 1) #25 comdat !dbg !2061 {
+define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET_T0_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1) #25 comdat !dbg !2061 {
   %4 = alloca i8, align 1
   %5 = alloca %class.VaryingWriter, align 32
   %6 = alloca %"struct.PrintInfo::Encoding4Varying", align 1
@@ -10036,7 +10036,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriter
   %22 = bitcast %class.VaryingWriter* %5 to i8*, !dbg !2063
   %23 = bitcast %class.VaryingWriter* %1 to i8*, !dbg !2063
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %22, i8* align 32 %23, i64 64, i1 false), !dbg !2063, !tbaa.struct !197
-  %24 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %21, %class.VaryingWriter* byval align 32 %5, %"struct.PrintInfo::Encoding4Varying"* byval align 1 %6), !dbg !2064
+  %24 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %21, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %5, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1 %6), !dbg !2064
   br i1 %24, label %60, label %25, !dbg !2065
 
 ; <label>:25:                                     ; preds = %3
@@ -10044,7 +10044,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriter
   %27 = bitcast %class.VaryingWriter* %7 to i8*, !dbg !2067
   %28 = bitcast %class.VaryingWriter* %1 to i8*, !dbg !2067
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %27, i8* align 32 %28, i64 64, i1 false), !dbg !2067, !tbaa.struct !197
-  %29 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %26, %class.VaryingWriter* byval align 32 %7, %"struct.PrintInfo::Encoding4Varying"* byval align 1 %8), !dbg !2068
+  %29 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %26, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %7, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1 %8), !dbg !2068
   br i1 %29, label %60, label %30, !dbg !2069
 
 ; <label>:30:                                     ; preds = %25
@@ -10052,7 +10052,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriter
   %32 = bitcast %class.VaryingWriter* %9 to i8*, !dbg !2071
   %33 = bitcast %class.VaryingWriter* %1 to i8*, !dbg !2071
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %32, i8* align 32 %33, i64 64, i1 false), !dbg !2071, !tbaa.struct !197
-  %34 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %31, %class.VaryingWriter* byval align 32 %9, %"struct.PrintInfo::Encoding4Varying"* byval align 1 %10), !dbg !2072
+  %34 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %31, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %9, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1 %10), !dbg !2072
   br i1 %34, label %60, label %35, !dbg !2073
 
 ; <label>:35:                                     ; preds = %30
@@ -10060,7 +10060,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriter
   %37 = bitcast %class.VaryingWriter* %11 to i8*, !dbg !2075
   %38 = bitcast %class.VaryingWriter* %1 to i8*, !dbg !2075
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %37, i8* align 32 %38, i64 64, i1 false), !dbg !2075, !tbaa.struct !197
-  %39 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %36, %class.VaryingWriter* byval align 32 %11, %"struct.PrintInfo::Encoding4Varying"* byval align 1 %12), !dbg !2076
+  %39 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %36, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %11, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1 %12), !dbg !2076
   br i1 %39, label %60, label %40, !dbg !2077
 
 ; <label>:40:                                     ; preds = %35
@@ -10068,7 +10068,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriter
   %42 = bitcast %class.VaryingWriter* %13 to i8*, !dbg !2079
   %43 = bitcast %class.VaryingWriter* %1 to i8*, !dbg !2079
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %42, i8* align 32 %43, i64 64, i1 false), !dbg !2079, !tbaa.struct !197
-  %44 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %41, %class.VaryingWriter* byval align 32 %13, %"struct.PrintInfo::Encoding4Varying"* byval align 1 %14), !dbg !2080
+  %44 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %41, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %13, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1 %14), !dbg !2080
   br i1 %44, label %60, label %45, !dbg !2081
 
 ; <label>:45:                                     ; preds = %40
@@ -10076,7 +10076,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriter
   %47 = bitcast %class.VaryingWriter* %15 to i8*, !dbg !2083
   %48 = bitcast %class.VaryingWriter* %1 to i8*, !dbg !2083
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %47, i8* align 32 %48, i64 64, i1 false), !dbg !2083, !tbaa.struct !197
-  %49 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %46, %class.VaryingWriter* byval align 32 %15, %"struct.PrintInfo::Encoding4Varying"* byval align 1 %16), !dbg !2084
+  %49 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %46, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %15, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1 %16), !dbg !2084
   br i1 %49, label %60, label %50, !dbg !2085
 
 ; <label>:50:                                     ; preds = %45
@@ -10084,7 +10084,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriter
   %52 = bitcast %class.VaryingWriter* %17 to i8*, !dbg !2087
   %53 = bitcast %class.VaryingWriter* %1 to i8*, !dbg !2087
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %52, i8* align 32 %53, i64 64, i1 false), !dbg !2087, !tbaa.struct !197
-  %54 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %51, %class.VaryingWriter* byval align 32 %17, %"struct.PrintInfo::Encoding4Varying"* byval align 1 %18), !dbg !2088
+  %54 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %51, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %17, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1 %18), !dbg !2088
   br i1 %54, label %60, label %55, !dbg !2089
 
 ; <label>:55:                                     ; preds = %50
@@ -10092,7 +10092,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriter
   %57 = bitcast %class.VaryingWriter* %19 to i8*, !dbg !2091
   %58 = bitcast %class.VaryingWriter* %1 to i8*, !dbg !2091
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 32 %57, i8* align 32 %58, i64 64, i1 false), !dbg !2091, !tbaa.struct !197
-  %59 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIPv13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %56, %class.VaryingWriter* byval align 32 %19, %"struct.PrintInfo::Encoding4Varying"* byval align 1 %20), !dbg !2092
+  %59 = call zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIPv13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext %56, %class.VaryingWriter* byval(%class.VaryingWriter) align 32 %19, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1 %20), !dbg !2092
   br label %60, !dbg !2089
 
 ; <label>:60:                                     ; preds = %55, %50, %45, %40, %35, %30, %25, %3
@@ -10101,7 +10101,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail14switchEncodingI13VaryingWriter
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval align 32, %"struct.PrintInfo::Encoding4Varying"* byval align 1) #25 comdat !dbg !2094 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1) #25 comdat !dbg !2094 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -10127,7 +10127,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIb13Varyi
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval align 32, %"struct.PrintInfo::Encoding4Varying"* byval align 1) #25 comdat !dbg !2103 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1) #25 comdat !dbg !2103 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -10153,7 +10153,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIi13Varyi
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval align 32, %"struct.PrintInfo::Encoding4Varying"* byval align 1) #25 comdat !dbg !2112 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1) #25 comdat !dbg !2112 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -10179,7 +10179,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIj13Varyi
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval align 32, %"struct.PrintInfo::Encoding4Varying"* byval align 1) #25 comdat !dbg !2121 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1) #25 comdat !dbg !2121 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -10205,7 +10205,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIf13Varyi
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval align 32, %"struct.PrintInfo::Encoding4Varying"* byval align 1) #25 comdat !dbg !2130 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1) #25 comdat !dbg !2130 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -10231,7 +10231,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIx13Varyi
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval align 32, %"struct.PrintInfo::Encoding4Varying"* byval align 1) #25 comdat !dbg !2139 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1) #25 comdat !dbg !2139 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -10257,7 +10257,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIy13Varyi
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval align 32, %"struct.PrintInfo::Encoding4Varying"* byval align 1) #25 comdat !dbg !2148 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1) #25 comdat !dbg !2148 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193
@@ -10283,7 +10283,7 @@ define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingId13Varyi
 }
 
 ; Function Attrs: alwaysinline inlinehint nounwind
-define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIPv13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval align 32, %"struct.PrintInfo::Encoding4Varying"* byval align 1) #25 comdat !dbg !2157 {
+define internal zeroext i1 @_ZN9PrintInfo6detail21applyIfProperEncodingIPv13VaryingWriterNS_16Encoding4VaryingEEEbNS_8EncodingET0_T1_(i8 signext, %class.VaryingWriter* byval(%class.VaryingWriter) align 32, %"struct.PrintInfo::Encoding4Varying"* byval(%"struct.PrintInfo::Encoding4Varying") align 1) #25 comdat !dbg !2157 {
   %4 = alloca i1, align 1
   %5 = alloca i8, align 1
   store i8 %0, i8* %5, align 1, !tbaa !193